Matthieu Arzel

**Education** ------------- - HDR, University of South Brittany, 2021 - PhD in Electronics, Ecole Nationale Supérieure des Télécommunications (ENST) de Bretagne (France), 2006 - Engineer degree and DEA (MSc) of Electronics, Ecole Nationale Supérieure des Télécommunications (ENST) de Bretagne (France),2002 **Fields of expertise** ----------------------- ### Analogue/mixed integrated circuit architectures and low-power flexible Systems on Chip in the fields of - digital communications (power/area/throughput/accuracy/latency optimization of circuit architectures for digital transmitters and receivers) - artificial neural networks (design of architectures for mixed-signal custom ASICs and FPGAs) - medical engineering (design of low-power embedded biomedical systems) ### High-speed digital reconfigurable circuits for digital communications, network security and machine learning - design of dedicated processors implemented on ASICs and FPGAs transferring data via (Q)SFP(+) and PCIe interfaces - test and evaluation of Xilinx and Intel solutions ### Iterative processing techniques for digital communications - design of iterative soft decoders for forward Error Correction codes such as Turbo codes, Low-Density Parity-check codes, Raptor codes, Cortex codes with fixed-point or stochastic arithmetic - implementation of iterative receivers **Professional experience** --------------------------- ### 2006-2021: Associate professor at Telecom Bretagne, and then IMT Atlantique Bretagne - Pays de la Loire 2021-today: Professor at IMT Atlantique Bretagne - Pays de la Loire - Supervisor of 18 PhD candidates - Co-Head of the Courses in the Department of Mathematical and Electrical Engineering - Technical Program Committee member of the IEEE International Symposium on Turbo Codes & Iterative Information Processing ’10, ’16, ’18 - Member of Lab-STICC (CNRS UMR 6285) / CACS/ Interaction between Algorithms and Silicon (IAS) Team - Reviewer for IEEE Transactions on Signal Processing, EURASIP Journal on Advances in Signal Processing,IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, IET Electronics Letters, IEEE Transactions on Communications, IEEE Communications Letters,IEEE ISCAS, IEEE NEWCAS, IEEE ICECS - Principal investigator of research activities with European Space Agency, French Research Agency and Cominlabs and of research contracts with companies (Orange Labs, EMC Norway, Widenorth Consulting, OVH, Huawei) ### 2005-2006: Research Engineer at TurboConcept (France) - Designer of IP modules for synchronization and error correction in digital receivers on FPGA.