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Matthieu Arzel
100
Documents
Identifiants chercheurs
matthieu-arzel- IdRef : 112376606
-
0000-0002-8774-7662
Présentation
**Education**
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- HDR, University of South Brittany, 2021
- PhD in Electronics, Ecole Nationale Supérieure des Télécommunications (ENST) de Bretagne (France), 2006
- Engineer degree and DEA (MSc) of Electronics, Ecole Nationale Supérieure des Télécommunications (ENST) de Bretagne (France),2002
**Fields of expertise**
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### Analogue/mixed integrated circuit architectures and low-power flexible Systems on Chip in the fields of
- digital communications (power/area/throughput/accuracy/latency optimization of circuit architectures for digital transmitters and receivers)
- artificial neural networks (design of architectures for mixed-signal custom ASICs and FPGAs)
- medical engineering (design of low-power embedded biomedical systems)
### High-speed digital reconfigurable circuits for digital communications, network security and machine learning
- design of dedicated processors implemented on ASICs and FPGAs transferring data via (Q)SFP(+) and PCIe interfaces
- test and evaluation of Xilinx and Intel solutions
### Iterative processing techniques for digital communications
- design of iterative soft decoders for forward Error Correction codes such as Turbo codes, Low-Density Parity-check codes, Raptor codes, Cortex codes with fixed-point or stochastic arithmetic
- implementation of iterative receivers
**Professional experience**
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### 2006-2021: Associate professor at Telecom Bretagne, and then IMT Atlantique Bretagne - Pays de la Loire
2021-today: Professor at IMT Atlantique Bretagne - Pays de la Loire
- Supervisor of 18 PhD candidates
- Co-Head of the Courses in the Department of Mathematical and Electrical Engineering
- Technical Program Committee member of the IEEE International Symposium on Turbo Codes & Iterative Information Processing ’10, ’16, ’18
- Member of Lab-STICC (CNRS UMR 6285) / CACS/ Interaction between Algorithms and Silicon (IAS) Team
- Reviewer for IEEE Transactions on Signal Processing, EURASIP Journal on Advances in Signal Processing,IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, IET Electronics Letters, IEEE Transactions on Communications, IEEE Communications Letters,IEEE ISCAS, IEEE NEWCAS, IEEE ICECS
- Principal investigator of research activities with European Space Agency, French Research Agency and Cominlabs and of research contracts with companies (Orange Labs, EMC Norway, Widenorth Consulting, OVH, Huawei)
### 2005-2006: Research Engineer at TurboConcept (France)
- Designer of IP modules for synchronization and error correction in digital receivers on FPGA.
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Simulating Aerial Event-based Environment: Application to Car DetectionEuropean Robotics Forum 2024, Lorenzo Marconi, Mar 2024, Rimini, Italy
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Compression de réseaux de neurones pour l'apprentissage fédéréXXIXème Colloque GRETSI, Aug 2023, Grenoble, France
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Pipelined Architecture for a Semantic Segmentation Neural Network on FPGAICECS 2023: IEEE 30th International Conference on Electronics, Circuits and Systems, Dec 2023, Istanbul, Turkey. ⟨10.1109/ICECS58634.2023.10382715⟩
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Federated learning compression designed for lightweight communicationsICECS 2023: IEEE 30th International Conference on Electronics, Circuits and Systems, Dec 2023, Istanbul, Turkey. ⟨10.1109/ICECS58634.2023.10382717⟩
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Neural Networks as Catalysts for Enhanced Lossless Compression in Satellite CommunicationsInternational Conference on Emerging Technologies for Communication, ICETC 2023, Nov 2023, Sapporo, Japan
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Investigating the Not-So-Obvious Effects of Structured PruningICML 2022 - Hardware-aware efficient training (HAET), Jul 2022, Baltimore, United States
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DWT Collusion Resistant Video Watermarking Using Tardos Family CodesFifth IEEE International Conference on Image Processing, Applications and Systems (IPAS 2022), Dec 2022, Genoa, Italy. ⟨10.1109/IPAS55744.2022.10053023⟩
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Leveraging Structured Pruning of Convolutional Neural NetworksSiPS 2022: IEEE Workshop on Signal Processing Systems, Nov 2022, Rennes, France. pp.1-6, ⟨10.1109/SiPS55645.2022.9919253⟩
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Élagage de réseaux profond de neurones par dégradation sélective des pondérationsGRETSI 2022 : 28ème colloque du Groupement de Recherche en Traitement du Signal et des Images, Sep 2022, Nancy, France
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Energy Consumption Analysis of pruned Semantic Segmentation Networks on an Embedded GPUSYSINT 2022: International Conference on System-Integrated Intelligence, Springer, Sep 2022, Genova, Italy. pp.553-563, ⟨10.1007/978-3-031-16281-7_52⟩
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Shuffled Decoding of Serial Concatenated Convolutional CodesISTC 2021: 11th International Symposium on Topics in Coding, Aug 2021, Montreal, Canada. ⟨10.1109/ISTC49272.2021.9594068⟩
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Quantized Guided Pruning for Efficient Hardware Implementations of Deep Neural NetworksNEWCAS 2020 : 18th IEEE International New Circuits and Systems Conference, Jun 2020, Montréal, Canada. pp.206-209, ⟨10.1109/NEWCAS49341.2020.9159769⟩
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User Terminal Wideband Modem for Very High Throughput SatellitesICSSC 2019 : 37th International Communications Satellite Systems Conference, Oct 2019, Okinawa, Japan
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Efficient Hardware Implementation of Incremental Learning and Inference on ChipNEWCAS 2019 : 17th IEEE International New Circuits and Systems Conference, Jun 2019, Munich, Germany. ⟨10.1109/NEWCAS44328.2019.8961310⟩
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40 Gop/S/mm² Fixed-Point Operators for Brain Computer Interface in 65nm CMOS2018 IEEE International Symposium on Circuits and Systems (ISCAS), May 2018, Florence, Italy. ⟨10.1109/ISCAS.2018.8351028⟩
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A fully flexible circuit implementation of clique-based neural networks in 65-nm CMOSISCAS 2018 : IEEE International Symposium on Circuits and Systems (ISCAS), May 2018, Firenze, Italy. ⟨10.1109/ISCAS.2018.8350954⟩
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How to apprehend leadership related skills in a project management experiment?SEFI 2017: 45th Conference on Education Excellence For Sustainable Development, Sep 2017, Azores, Portugal. pp.536-543
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A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architectureISCAS 2017 : IEEE International Symposium on Circuits and Systems, May 2017, Baltimore, United States. pp.1 - 4, ⟨10.1109/ISCAS.2017.8050658⟩
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Budget Restricted Incremental Learning with Pre-Trained Convolutional Neural Networks and Binary Associative MemoriesSIPS 2017 : IEEE International Workshop on Signal Processing Systems, Oct 2017, Lorient, France. pp.1 - 4, ⟨10.1109/SiPS.2017.8109978⟩
Communication dans un congrès
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Implantation en virgule fixe d'un opérateur de calcul d'inverse à base de Newton-Raphson, sans normalisation et sans bloc mémoireGRETSI 2017 : 26ème colloque du Groupement de Recherche en Traitement du Signal et des Images, Sep 2017, Juan-Les-Pins, France
Communication dans un congrès
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Architecture de détecteur MIMO-BP itératif associé à un décodeur LDPC non binaireGRETSI 2017 : 26ème colloque du Groupement de Recherche en Traitement du Signal et des Images, Sep 2017, Juan Les Pins, France
Communication dans un congrès
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A Sub-nJ CMOS ECG Classifier for Wireless Smart SensorEMBC 2017 : 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Jul 2017, Jeju, South Korea. pp.3840 - 3843, ⟨10.1109/EMBC.2017.8037694⟩
Communication dans un congrès
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Finding All Matches in a Database using Binary Neural NetworksCOGNITIVE 2017: The Ninth International Conference on Advanced Cognitive Technologies and Applications, Feb 2017, Athènes, Greece. pp.59-64
Communication dans un congrès
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Combining FPGAs and processors for high-throughput forensicsCNS 2017 : IEEE Conference on Communications and Network Security, Oct 2017, Las Vegas, United States. ⟨10.1109/CNS.2017.8228684⟩
Communication dans un congrès
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An ultra-low power iterative clique-based neural network integrated in 65-nm CMOSNEWCAS 2017 : 15th IEEE International New Circuits and Systems Conference, Jun 2017, Strasbourg, France. pp.5 - 8, ⟨10.1109/NEWCAS.2017.8010091⟩
Communication dans un congrès
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Incremental Learning on ChipGlobalSIP 2017 : 5th IEEE Global Conference on Signal and Information Processing, Nov 2017, Montréal, Canada. ⟨10.1109/GlobalSIP.2017.8309068⟩
Communication dans un congrès
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A scaling-less Newton-Raphson pipelined implementation for a fixed-point inverse square root operatorNEWCAS 2017 : 15th IEEE International New Circuits and Systems Conference, Jun 2017, Strasbourg, France. ⟨10.1109/NEWCAS.2017.8010129⟩
Communication dans un congrès
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Open-source flexible packet parser for high data rate agile network probeCNS 2017 : IEEE Conference on Communications and Network Security, Oct 2017, Las Vegas, États-Unis. ⟨10.1109/CNS.2017.8228685⟩
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Boosting advanced skills in project management thanks to complex human and technical situationsSEFI 2016: 44th European Society for Engineering Education annual conference, Sep 2016, Tampere, Finland. pp.1-11
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Soft detector architecture based on Belief Propagation for MIMO systemsDASIP 2016 : Conference on Design and Architectures for Signal and Image Processing, Oct 2016, Rennes, France. pp.1 - 4
Communication dans un congrès
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Autoreloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAsDSD 2016 : Euromicro Conference on Digital System Design, Aug 2016, Limassol, Cyprus. pp.14 - 21, ⟨10.1109/DSD.2016.92⟩
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Toward sub-pJ per classification in Body Area Sensor NetworksNEWCAS 2016 : 14th IEEE International on New Circuits and Systems, Jun 2016, Vancouver, Canada. pp.1 - 4, ⟨10.1109/NEWCAS.2016.7604764⟩
Communication dans un congrès
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Architecture d'un détecteur MIMO souple basé sur l'algorithme de propagation de croyanceGDR SoC-SiP 2016 : colloque National du Groupe de Recherche System on Chip -System in Package, Jun 2016, Nantes, France
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Analyse d'une formation à la conduite de projets selon une grille de maturité de processusQPES 2015 : Colloque Questions de pédagogies dans l'enseignement supérieur. Innover : pourquoi et comment ?, Jun 2015, Brest, France. pp.125-130
Communication dans un congrès
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Design of analog subthreshold encoded neural network circuit in sub-100nm CMOSIJCNN 2015 : IEEE International Joint Conference on Neural Networks, Jul 2015, Killarney, Ireland. pp.1 - 7, ⟨10.1109/IJCNN.2015.7280672⟩
Communication dans un congrès
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Algorithme de détection à très faible complexité pour des systèmes MIMO basés sur la propagation de croyanceGRETSI 2015 : 25ème colloque du Groupement de Recherche en Traitement du Signal et des Images, Sep 2015, Lyon, France
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Score distribution as a tool to reveal group dynamics in student projects?SEFI 2015 : Annual Conference of the European Society for Engineering Education, Jun 2015, Orléans, France. pp.111 - 111
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Study of fibrosis induced by an implanted medical deviceHandicap, Jun 2014, Paris, France
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Introducing complexity into project management through multi-stakeholder interactionsSEFI 2014 : 42th annual conference, Sep 2014, Birmingham, United Kingdom. pp.135 - 135
Communication dans un congrès
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Low-Complexity LDPC-coded Iterative MIMO Receiver Based on Belief Propagation algorithm for DetectionISTC 2014 : 8th International Symposium on Turbo Codes and Iterative Information Processing, Aug 2014, Bremen, Germany. pp.213 - 217, ⟨10.1109/ISTC.2014.6955116⟩
Communication dans un congrès
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Low-Complexity LDPC-coded Iterative MIMO Receiver Based on Belief Propagation algorithm for DetectionGDR SoCSiP-ISIS 2014 : journée thématique Architectures de Codes Correcteurs d'Erreurs, Nov 2014, Plouzané, France
Communication dans un congrès
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Low-Complexity layered BP-based Detection and Decoding for a NB-LDPC Coded MIMO SystemICC 2014 : IEEE International Conference on Communications, Jun 2014, Sydney, Australia. pp.5107 - 5112, ⟨10.1109/ICC.2014.6884131⟩
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Symbol-based BP Detection for MIMO Systems associated with Non-Binary LDPC CodesWCNC 2014 : IEEE Wireless Communications and Networking Conference, Apr 2014, Istanbul, Turquie. pp.212 - 217, ⟨10.1109/WCNC.2014.6951949⟩
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Study of a Cosmic Ray Impact on Combinatorial Logic Circuits of an 8bit SAR ADC in 65nm CMOS TechnologyMWSCAS 2013 : IEEE 56th International Midwest Symposium on Circuits and Systems, Jul 2013, Columbus, United States
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Analog implementation of encoded neural networksISCAS 2013 : IEEE International Symposium on Circuits and Systems, May 2013, Beijing, China. pp.1 - 4
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Accélération matérielle pour le traitement de trafic sur FPGA15èmes Rencontres Francophones sur les Aspects Algorithmiques des Télécommunications (AlgoTel), May 2013, Pornic, France. pp.1-4
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PAPR reduction using contiguous-tone Tone Reservation technique in optical OFDM IMDD transmissionsOFC/NFOEC 2013 : Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013, Mar 2013, Anaheim, United States
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Analog Encoded Neural Network for Power Management in MPSoCNEWCAS 2013 : proceedings of the 11th IEEE international NEWCAS conference, Jun 2013, Paris, France. pp.1 - 4
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Flexible, extensible, open-source and affordable FPGA-based traffic generatorHPDC 2013 : 22nd International ACM Symposium on High Performance Parallel and Distributed Computing, Jun 2013, New-York, United States
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Réception itérative MIMO basée sur la propagation de croyance et des codes LDPC non-binairesGRETSI 2013 : 24ème colloque du Groupement de Recherche en Traitement du Signal et des Images, Sep 2013, Brest, France
Communication dans un congrès
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Stochastic Chase Decoder for Reed-Solomon CodesNEWCAS 2012, Jun 2012, Montreal, Canada
Communication dans un congrès
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On the Performance of Timing Synchronization Techniques for Optical OFDM IMDD TransmissionIPC 2012: IEEE Photonics conference, Sep 2012, Burlingame, Ca, United States. pp.179 - 180
Communication dans un congrès
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Hardware Acceleration of SVM-Based Traffic Classification on FPGAIWCMC TRAC: International Wireless Communications and Mobile Computing Conference, International Workshop on TRaffic Analysis and Classification, Aug 2012, Limassol, Cyprus
Communication dans un congrès
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Multi-standard Trellis-based FEC DecoderDASIP 2012 : Conference on Design & Architectures for Signal & Image Processing, Oct 2012, Karlsruhe, Germany
Communication dans un congrès
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Adapted scheduling of QC-LDPC decoding for multistandard receiversInternational Symposium on Turbo Codes & Iterative Information, Aug 2012, Gothenburg, Sweden. pp.111 - 115, ⟨10.1109/ISTC.2012.6325209⟩
Communication dans un congrès
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An analog core computing the center of pressure in in a knee replacement prosthesisIEEE NEWCAS 2011: IEEE 9th International conference on New Circuits and Systems Conference, Jun 2011, Bordeaux, France. pp.105 - 108, ⟨10.1109/NEWCAS.2011.5981230⟩
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Design and FPGA Implementation of Stochastic Turbo DecoderNEWCAS 2011, Jun 2011, Bordeaux, France. pp.21-24
Communication dans un congrès
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In-vivo polyethylene wear and knee prosthesis longevity estimationITAB 2010: IEEE International Conference on Information Technology and Applications in Biomedicine, Nov 2010, Corfou, Greece. pp.1-4, ⟨10.1109/ITAB.2010.5687610⟩
Communication dans un congrès
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Decreasing the effects of BJT's parasitics of computing cells for analog decoders6th Symposium of Turbo codes and related topics, Sep 2010, Brest, France. pp.261 - 264
Communication dans un congrès
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Ligament imbalance metrics and an autonomous measurement system for post TKA32nd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Aug 2010, Buenos Aires, Argentina. pp.6417 - 6420
Communication dans un congrès
hal-00540867v1
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Trade-off between surface, biasing current and performance of an analog turbo decoderIEEE joint conference NEWCAS-TAISA'09, June 28 - July 01, Toulouse, France, Jun 2009, Toulouse, France. pp.199 - 202
Communication dans un congrès
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A ligament laxity telemetry system architecture for a knee replacement prosthesis2nd International Symposium on Applied Sciences in Biomedical and Communication Technologies, Nov 2009, Bratislava, Slovakia. pp.1 - 6
Communication dans un congrès
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Design and implementation of a MIMO channel emulator onto FPGA deviceIWS'09 : 1XV proyecto Iberchip, Mar 2009, Buenos Aires, Argentina
Communication dans un congrès
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Effect of BJT's parasitics on computing cells for analog decodersNEWCAS-TAISA, 22-25 juin 2008, Montréal, Québec, Canada, Jun 2008, Montréal, Canada
Communication dans un congrès
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Design and test of a 0.25um-BICMOS double binary analogue APP DecoderADW ΄06 : 5th Analog Decoding Workshop, June 5-6, Torino, Italy, Jun 2006, Torino, Italy. pp.35 - 38
Communication dans un congrès
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Semi-Iterative Analog Turbo DecodingISCAS 2006 : International Symposium on Circuits and Systems, Kos, Greece, May 21-24, May 2006, Kos, Greece. pp.3562 - 3565
Communication dans un congrès
hal-01809339v1
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Semi-iterative analogue turbo decodingADW 2005 : 4th Analog Decoding Workshop, June 16-17, Rennes, France, Jun 2005, Rennes, France
Communication dans un congrès
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Analog slice turbo decodingISCAS 2005 : IEEE International Symposium on Circuits And Systems, Kobé, Japan, May 23-26, May 2005, Kobé, Japan. pp.332 - 335, ⟨10.1109/ISCAS.2005.1464592⟩
Communication dans un congrès
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Décodage analogique de codes duo-binaires DVB-RCSISIVC'04 : 2nd International Symposium on Image/Video Communications over fixed and mobile networks, 7-9 juillet Brest, France, Jul 2004, Brest, France
Communication dans un congrès
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Analogue decoding of duo-binary codesISITA 2004 : International Symposium on Information Theory and its Applications, 10-13 octobre, Parme, Italie, Oct 2004, Parme, Italy
Communication dans un congrès
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Turbo décodage de code produit haut débit utilisant un code BCH étenduGRETSI' 03 : 19ème colloque sur le traitement du signal et des images, 8-11 septembre, Paris, Sep 2003, Paris, France. pp.349 - 352
Communication dans un congrès
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Compression Study on Federated LearningAssemblée Générale 2023 du GdR ISIS, May 2023, Lyon, France
Poster de conférence
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Accélération matérielle pour l'imagerie cérébrale par EEG13ème Colloque du GDR SoC/SiP, Jun 2017, Bordeaux, France
Poster de conférence
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Ouessant: Flexible Integration of Dedicated Coprocessors in Systems On ChipDATE 2016 : Design, Automation & Test in Europe Conference & Exhibition , Mar 2016, Dresden, Germany. pp.1493 - 1496, 2016
Poster de conférence
hal-01343408v1
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An efficient MIMO receiver based on BP algorithm with truncated message-passingGDR SoC-SiP 2014 : 9ème colloque national du GDR SoC-SiP du CNRS, Jun 2014, Paris, France. 2014
Poster de conférence
hal-01061840v1
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Codes and Turbo CodesSpringer-Verlag, pp.400, 2010, IRIS international series, 9782817800387
Ouvrages
hal-01170419v1
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Codes et turbocodes (sous la direction de Claude Berrou)Springer, pp.397, 2007, Iris, Iris, 978-2-287-32739-1
Ouvrages
hal-01801570v1
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Decoding of series-concatenated turbo codesFrance, Patent n° : WO2022234196. 2022
Brevet
hal-03321490v1
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Procédé de codage de données à au moins deux étapes d'encodage à et au moins une étape de permutation, dispositif de codage, programme d'ordinateur et signal correspondantsFrance, N° de brevet: 2 941 829. 7662. 2010
Brevet
hal-01170863v1
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Procédé et dispositif de décodage de codes à roulettesFrance, N° de brevet: FR2883121. 2283. 2006
Brevet
hal-01807308v1
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Quantized Guided Pruning for Efficient Hardware Implementations of Convolutional Neural Networks2018
Pré-publication, Document de travail
hal-01965304v1
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Traiter et transmettre l'information à hautdébit, à énergie réduite, avec flexibilité : le grand écart dans trois directionsArchitectures Matérielles [cs.AR]. Université de Bretagne Sud, 2021
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