Mots-clés

Co-auteurs

Projets Européen

Identifiants chercheur

  • IdHAL : marie-lise-flottes
Nombre de documents

172

Publications de Marie-Lise Flottes


Article dans une revue20 documents

  • Jean Da Rolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Test versus Security: Past and Present. IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2014, pp.13. <http://www.computer.org/csdl/trans/ec/preprint/06733305-abs.html>. <10.1109/TETC.2014.2304492>. <lirmm-00989627>
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS. Microelectronics Reliability, Elsevier, 2014, 54 (9-10), pp.2289-2294. <10.1016/j.microrel.2014.07.151>. <emse-01094805>
  • Jean Da Rolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Test versus Security: Past and Present. IEEE Transactions on Emerging Topics in Computing, Institute of Electrical and Electronics Engineers, 2014, 2 (1), pp.50-62. <http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6733305>. <10.1109/TETC.2014.2304492>. <lirmm-01075405>
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Multi-Level Ionizing-Induced Transient Fault Simulator. Information Security Journal: A Global Perspective, Taylor & Francis, 2014, 22 (5-6), pp.251-264. <http://www.tandfonline.com/doi/abs/10.1080/19393555.2014.891280#.VEEP7tTLc4l>. <10.1080/19393555.2014.891280>. <lirmm-01075393>
  • Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis. Information Security Journal: A Global Perspective, Taylor & Francis, 2014, Trustworthy Manufacturing and Utilization of Secure Devices, 22 (5-6), pp.226-236. <10.1080/19393555.2014.891277>. <lirmm-00991362>
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. Microelectronics Reliability, Elsevier, 2013, European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, 53 (9), pp.1320-1324. <10.1016/j.microrel.2013.07.069>. <emse-01100723>
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Novel Differential Scan Attack on Advanced DFT Structures. Transactions on Design Automation of Electronic Systems, Association for Computing Machinery, 2013, 18 (4), pp.58. <10.1145/2505014>. <lirmm-01075410>
  • Jean Da Rolt, Marie-Lise Flottes, Amitabh Das, Santosh Ghosh, Stefaan Seys, et al.. Secure JTAG implementation using Schnorr Protocol. Journal of Electronic Testing, Springer Verlag, 2013, 29 (2), pp.193-209. <lirmm-00837904>
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre. A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic. Journal of Electronic Testing, Springer Verlag, 2013, pp.001-010. <10.1007/s10836-013-5359-y>. <lirmm-00838389>
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Thwarting Scan-Based Attacks on Secure-ICs with On-Chip Comparison. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2013, 22 (4), pp.001-004. <10.1109/TVLSI.2013.2257903>. <lirmm-00841650>
  • Jean Da Rolt, Amitabh Das, Santos Ghosh, Giorgio Di Natale, Marie-Lise Flottes, et al.. Scan attacks on side-channel and fault attack resistant public-key implementations. Journal of Cryptographic Engineering, Springer, 2012, 2 (4), pp.207-219. <10.1007/s13389-012-0045-z>. <lirmm-00805687>
  • Rodrigo Possamai Bastos, Frank Sill Torres, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Novel Transient-Fault Detection Circuit Featuring Enhanced Bulk Built-in Current Sensor with Low-Power Sleep Mode. Microelectronics Reliability, Elsevier, 2012, 52 (9-10), pp.1781-1786. <10.1016/j.microrel.2012.06.149>. <lirmm-00715117>
  • Jean Da Rolt, Amitabh Das, Santosh Ghosh, Giorgio Di Natale, Marie-Lise Flottes, et al.. Scan Attacks on Side-channel and Fault Attack Resistant Public-key Implementations. Journal of Cryptographic Engineering, Springer, 2012, 2 (4), pp.207-219. <10.1007/s13389-012-0045-z>. <lirmm-01075412>
  • Giorgio Di Natale, Doulcier Marion, Marie-Lise Flottes, Bruno Rouzeyre. A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard. Journal of Electronic Testing, Springer Verlag, 2009, 25 (4-5), pp.269-278. <10.1007/s10836-009-5106-6>. <lirmm-00423026>
  • Béatrice Pradarelli, Laurent Latorre, Marie-Lise Flottes, Yves Bertrand, Pascal Nouet. Remote Labs for Industrial IC Testing. IEEE Transactions on Learning Technologies, Institute of Electrical and Electronics Engineers, 2009, 2 (4), pp.304-311. <10.1109/TLT.2009.46>. <lirmm-00435903>
  • Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. Self-Test Techniques for Crypto-Devices. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2009, 18 (2), pp.329-333. <10.1109/TVLSI.2008.2010045>. <lirmm-00365359>
  • David Hely, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Securing Scan Control in Crypto Chips. Journal of Electronic Testing, Springer Verlag, 2007, 23 (5), pp.457-464. <10.1007/s10836-007-5000-z>. <lirmm-00186353>
  • Franc Novak, A. Biasizzo, Yves Bertrand, Marie-Lise Flottes, L. Balado, et al.. Academic Network for Microelectronic Test Education. International Journal of Engineering Education, Tempus Publications, 2007, 23 (6), pp.1245-1253. <http://www.ijee.dit.ie/contents/c230607.html>. <lirmm-00195573>
  • Marie-Lise Flottes, Christian Landrault, Aurélia Petitqueux. A Unified DFT Approach for BIST and External Test. Journal of Electronic Testing, Springer Verlag, 2003, 19 (1), pp.49-60. <lirmm-00269517>
  • Marie-Lise Flottes, Bruno Rouzeyre, Leo Volpe. Improving Datapath Testability by Modifying Controller Specification. VLSI Design, Hindawi Publishing Corporation, 2002, 15 (2), pp.491-498. <10.1080/1065514021000012101>. <lirmm-00268581>

Communication dans un congrès107 documents

  • Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. Using Outliers to Detect Stealthy Hardware Trojan Triggering?. IVSW: International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, France. IEEE International Verification and Security Workshop, 2016. <lirmm-01347119>
  • Manikandan Palanichamy, Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, et al.. Duplication-based Concurrent Detection of Hardware Trojans in Integrated Circuits. TRUDEVICE: Trustworthy Manufacturing and Utilization of Secure Devices, Mar 2016, Dresden, Germany. 5th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, 2016, <https://trudevice2016.eel.upc.edu/en>. <lirmm-01385551>
  • Papa-Sidy Ba, Sophie Dupuis, Manikandan Palanichamy, Marie-Lise Flottes, Giorgio Di Natale, et al.. Hardware Trust through Layout Filling: a Hardware Trojan Prevention Technique. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2016, Pittsburgh, United States. 2016, <http://www.isvlsi.org>. <10.1109/ISVLSI.2016.22>. <lirmm-01346529>
  • Mafalda Cortez, Said Hamdioui, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Hierarchical Secure DfT. TRUDEVICE: Secure Hardware and Security Evaluation, Sep 2015, St Malo, France. TRUDEVICE 2015 – 4TH WORKSHOP ON SECURE HARDWARE AND SECURITY EVALUATION. <lirmm-01234095>
  • Papa-Sidy Ba, Palanichamy Manikandan, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, et al.. Hardware Trojan Prevention using Layout-Level Design Approach. IEEE. ECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. Proceedings of the 2015 European Conference on Circuit Theory and Design (ECCTD), <10.1109/ECCTD.2015.7300093>. <lirmm-01234072>
  • Stephan De Castro, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Sensitivity to fault laser injection: a comparison between 28nm bulk and FD-SOI technology. TRUDEVICE: Secure Hardware and Security Evaluation, Sep 2015, Saint-Malo, France. 2015. <lirmm-01234094>
  • Raphael Viera, Rodrigo Possamai Bastos, Jean-Max Dutertre, Olivier Potin, Marie-Lise Flottes, et al.. Validation Of Single BBICS Architecture In Detecting Multiple Faults. ATS: Asian Test Symposium, Nov 2015, Mumbai, India. 24th IEEE Asian Test Symposium. <https://www.ee.iitb.ac.in/ats15/>. <lirmm-01234067>
  • Stephan De Castro, Jean-Max Dutertre, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Figure of merits of 28nm Si technologies for implementing laser attack resistant security dedicated circuits. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. 2015, Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). <10.1109/ISVLSI.2015.76>. <emse-01227138>
  • Sophie Dupuis, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Papa-Sidy Ba. New Testing Procedure for Finding Insertion Sites of Stealthy Hardware Trojans. DATE: Design, Automation and Test in Europe, Mar 2015, Grenoble, France. IEEE, 2015. <lirmm-01141619>
  • Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, et al.. 3D DFT Challenges and Solutions. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. pp.603-608, Proceedings of 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). <10.1109/ISVLSI.2015.11>. <lirmm-01234076>
  • Mafalda Cortez, Said Hamdioui, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Multi-segment Enhanced Scan-chains for Secure ICs. TRUDEVICE: Secure Hardware and Security Evaluation, Sep 2015, Saint-Malo, France. 4th workshop on Secure Hardware and Security Evaluation, 2015. <lirmm-01276304>
  • Marie-Lise Flottes, Sophie Dupuis, Papa-Sidy Ba, Bruno Rouzeyre. On the limitations of logic testing for detecting Hardware Trojans Horses. DTIS: Design & Technology of Integrated Systems in Nanoscale Era, Apr 2015, Naples, Italy. IEEE, Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2015 10th International Conference on, 2015, <10.1109/DTIS.2015.7127362>. <lirmm-01257837>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche. Built-In Self-Test for Manufacturing TSV Defects before bonding. IEEE. VTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. 32nd IEEE VLSI Test Symposium (VTS) pp.1-6, 2014, <10.1109/VTS.2014.6818771>. <lirmm-00989682>
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Customized Cell Detector for Laser-Induced-Fault Detection. IOLTS'2014: 20th International On-Line Testing Symposium, Jul 2014, Girona, Spain. pp.37-42, <10.1109/IOLTS.2014.6873669>. <lirmm-01119576>
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Layout-Aware Laser Fault Injection Simulation and Modeling: from physical level to gate level. DTIS'2014: 9th International Conference on Design & Technology of Integrated Systems, May 2014, Santorin, Greece. IEEE, <10.1109/DTIS.2014.6850665>. <lirmm-01119592>
  • Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, et al.. 2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2014, Tampa, Florida, United States. pp.386-391, 2014, Proceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). <10.1109/ISVLSI.2014.83>. <lirmm-01119605>
  • Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Simulating Laser Effects on ICs, from Physical Level to Gate Level: a comprehensive approach. TRUDEVICE'2014: Test and Fault Tolerance for Secure Devices, May 2014, Paderborn, Germany. 2014. <lirmm-01119614>
  • Jean-Max Dutertre, Stephan De Castro, Alexandre Sarafianos, Noémie Boher, Bruno Rouzeyre, et al.. Laser attacks on integrated circuits: from CMOS to FD-SOI. Design and Technology of Integrated Systems in Nanoscale Era (DTIS), May 2014, Santorin, Greece. <10.1109/DTIS.2014.6850664>. <emse-01099042>
  • Regis Leveugle, Paolo Maistri, Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, et al.. Laser-induced Fault Effects in Security-dedicated Circuits. International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2014, Mexico, Mexico. <emse-01099022>
  • Sophie Dupuis, Papa-Sidy Ba, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware Trojans. IOLTS'14: 20th International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Catalunya, Spain. IEEE, pp.49-54, 2014, <http://tima.imag.fr/conferences/IOLTS/iolts14/>. <lirmm-01025275>
  • Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre, et al.. Laser-Induced Fault Effects in Security-Dedicated Circuits. Luc Claesen; Maria-Teresa Sanz-Pascual; Ricardo Reis; Arturo Sarmiento-Reyes. VLSI-SoC: Very Large Scale Integration - System on a Chip, Oct 2014, Playa del Carmen, Mexico. 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration - System on a Chip, AICT-464, pp.220-240, 2015, IFIP Advances in Information and Communication Technology. <10.1007/978-3-319-25279-7_12>. <hal-01383737>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche. TSVs Pre-Bond Testing: a test scheme for capturing BIST responses. 3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, United States. IEEE, Fourth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits 3D-Test in conjunction with ITC / Test Week 2013 September 12-13, 2013 - Disneyland Hotel – Anaheim, California, USA, 2013, <http://www.pld.ttu.ee/3dtest/past_events/2013/>. <lirmm-00989707>
  • Hakim Zimouche, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale. A BIST Method for TSVs Pre-Bond Test. IDT'13: 8th IEEE International Design & Test Symposium, Dec 2013, Marrakesh, Morocco. pp.1-6, 2013, <http://idtsymposium.org/>. <10.1109/IDT.2013.6727081>. <lirmm-00989727>
  • Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, et al.. 3D Design For Test Architectures Based on IEEE P1687. 3D-TEST'13: Fourth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, California, United States. 2013. <lirmm-00989717>
  • Rodrigo Possamai Bastos, Frank Sill Torres, Jean-Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, et al.. A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2013, Karlsruhe, Germany. 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, pp.157-163, 2013, <http://www.patmos-conf.org/>. <10.1109/PATMOS.2013.6662169>. <lirmm-00968621>
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. ESREF: European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Sep 2013, Arcachon, France. IEEE Computer Society, 24th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, pp.B3c-2 #68, 2013. <hal-00872705>
  • Rodrigo Possamai Bastos, Frank Sill Torres, Jean-Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, et al.. A Bulk Built-in Sensor for Detection of Fault Attacks. HOST: Hardware Oriented Security and Trust, Jun 2013, Austin, TX, United States. IEEE International Symposium on Hardware Oriented Security and Trust, pp.51-54, 2013, <10.1109/HST.2013.6581565>. <hal-00871009>
  • Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Identification of Hardware Trojans triggering signals. First Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, May 2013, Avignon, France. 2013, <http://trudevice.com/Workshop/>. <lirmm-00991360>
  • Yassine Fkih, Pascal Vivet, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A 3D IC BIST for pre-bond test of TSVs using Ring Oscillators. NEWCAS: New Circuits and Systems, Jun 2013, Paris, France. IEEE, 11th International International New Circuits and Systems Conference, pp.001-004, 2013, <http://www.newcas2013.org/>. <lirmm-00838524>
  • Rodolphe Giroudeau, Florent Hernandez, Michel Gendreau, Marie-Lise Flottes, Giorgio Di Natale, et al.. Circuits intégrés en 3D. ROADEF: Recherche Opérationnelle et d'Aide à la Décision, Apr 2012, Angers, France. 13e congrès annuel de la Société française de Recherche Opérationnelle et d’Aide à la Décision, 2012, <http://roadef2012.ima.uco.fr/index.htm>. <lirmm-00805058>
  • Jean Da Rolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, et al.. A New Scan Attack on RSA in Presence of Industrial Countermeasures. Third International Workshop on Constructive Side-Channel Analysis and Secure Design, May 2012, Darmstadt, Germany. Springer, 7275, pp.89-104, 2012, Lecture Notes in Computer Science (LNCS). <http://cosade.cased.de/>. <lirmm-00719986>
  • Rodrigo Possamai Bastos, Frank Sill Torres, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode. ESREF: European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Oct 2012, Cagliari, Italy. 23rd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, 2012. <hal-00867864>
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Are Advanced DfT Structures Sufficient for Preventing Scan-Attacks?. VTS'12: 30th IEEE VLSI Test Symposium, Apr 2012, Maui, Hawai, United States. IEEE, pp.246-251, 2012, IEEE Catalog number : CFP12029-CDR. <http://www.tttc-vts.org/public_html/new/2012/index.php>. <lirmm-00694536>
  • Jean Da Rolt, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Amitabh Das, et al.. A Scan-based Attack on Elliptic Curve Cryptosystems in presence of Industrial Design-for-Testability Structures. IEEE International Symposium on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, United States. http://www.dfts.org/, 2012. <lirmm-00744472>
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. On-Chip Comparison for Testing Secure ICs. DCIS'2012: Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.112-117, 2012. <lirmm-00795205>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka, Denis Real. Power Consumption Traces Realignment to Improve Differential Power Analysis. DDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Germany. pp.201-206, 2011. <lirmm-00592005>
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Scan Attacks and Countermeasures in Presence of Scan Response Compactors. ETS: European Test Symposium, May 2011, Trondheim, Norway. 16th IEEE European Test Symposium, pp.19-24, 2011, <http://www.ieee-ets.org/>. <10.1109/ETS.2011.30>. <lirmm-00647062>
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. How to Sample Results of Concurrent Error Detection Schemes in Transient Fault Scenarios?. RADECS: Radiation and Its Effects on Components and Systems, Sep 2011, Sevilla, Spain. IEEE, 12th European Conference on Radiation and Its Effects on Components and Systems, pp.635-642, 2012, <http://www.radecs.net/>. <10.1109/RADECS.2011.6131361>. <lirmm-00701776>
  • Jean Da Rolt, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. New side-channel attack against scan chains. 9th CryptArchi Workshop (2011), Jun 2011, Bochum, Germany. pp.2, 2011, <http://labh-curien.univ-st-etienne.fr/cryptarchi/>. <lirmm-00648575>
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Timing Issues for an Efficient Use of Concurrent Error Detection Codes. LATW'11: 12th IEEE Latin American Test Workshop, Mar 2011, Brazil. pp.1-6, 2011, <latw.tttc-events.org>. <10.1109/LATW.2011.5985933>. <lirmm-00627427>
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A New Bulk Built-in Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies. IEEE. DFT'2011: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2011, Vancouver, Canada. pp.302-308, 2011, <http://www.dfts.org/>. <10.1109/DFT.2011.15>. <lirmm-00701789>
  • Jean Da Rolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. New Security Threats Against Chips Containing Scan Chain Structures. HOST'11: IEEE International Symposium on Hardware-Oriented Security and Trust, San Diego, CA, United States. pp.105-110, 2011. <lirmm-00599690>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka. Waveforms re-Alignment to Improve DPA Attacks. CryptArchi'10: Cryptographic Architectures Embedded in Reconfigurable Devices, Jun 2010, Gif-sur-Yvette, France. 2010, <http://labh-curien.univ-st-etienne.fr/cryptarchi/workshop10/program.html>. <lirmm-00539994>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Ensuring High Testability without Degrading Security. DDECS'10: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Vienna, Austria. pp.6, 2010. <lirmm-00480710>
  • Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Evaluation of Concurrent Error Detection Techniques on the Advanced Encryption Standard. ETS: European Test Symposium, May 2010, Prague, Czech Republic. 15th IEEE European Test Symposium, 2010. <lirmm-00493247>
  • Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Evaluation of Concurrent Error Detection Techniques on the Advanced Encryption Standard. IOLTS'10: IEEE 16th International On-Line Testing Symposium, Jul 2010, Greece. pp.223 - 228, 2010, <http://tima.imag.fr/conferences/iolts/iolts10/index.htm>. <10.1109/IOLTS.2010.5560196>. <lirmm-00539232>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers. DELTA'10: Fifth IEEE International Symposium on Electronic Design, Test and Application, Jan 2010, Ho Chi Minh City, Vietnam. pp.256-261, 2010. <lirmm-00539993>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Tutorial on Design For Testability & Digital Security. IEEE 10th Latin American Test Workshop, 2009, Buzios, Brazil. 2009, <http://inf.ufrgs.br/latw/>. <lirmm-00407161>
  • Marie-Lise Flottes, Giorgio Di Natale, Paolo Maistri, Bruno Rouzeyre, Régis Leveugle. Ensuring High Testability without Degrading Security. ETS: European Test Symposium, May 2009, Seville, Spain. 14th IEEE European Test Symposium, 2009, <http://www.ieee-ets.org/>. <lirmm-00407163>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Execution Time Reduction of Differential Power Analysis Experiments. LATW'09: 10th Latin-American Test Workshop, Mar 2009, Armaçao dos Buzios, Brazil, pp.1-5, 2009, <10.1109/LATW.2009.4813819>. <lirmm-00367712>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An Integrated Validation Environment for Differential Power Analysis. DATE'09: Design Automation and Test in Europe, Nice, France. 2009. <lirmm-00407165>
  • Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. Low Cost Self-Test of Crypto-Devices. WDSN'08: 2nd Workshop on Dependable and Secure Nanocomputing, Jun 2008, Anchorage, Canada, United States. pp.41-46, 2008, <http://www.ece.cmu.edu/~koopman/dsn08/index.html>. <lirmm-00295108>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Observability of Stuck-at-Faults with Differential Power Analysis. LATW'08: IEEE Latin American Test Workshop, Feb 2008, Mexico. pp.N/A, 2008, <http://www-elec.inaoep.mx/latw2008/index.php>. <lirmm-00295498>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Reliable Architecture for Substitution Boxes in Integrated Cryptographic. DCIS'08: Conference on Design of Circuits and Integrated Systems, Nov 2008, CD-ROM, pp.27-32, 2008. <lirmm-00363783>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An Integrated Validation Environment for Differential Power Analysis. SAME'08: Sophia-Antipolis Forum on MicroElectronics 2008, Sep 2008, Sophia-Antipolis, France. 2008. <lirmm-00363796>
  • Isabelle Vogel, Marie-Lise Flottes, Christian Landrault. Initialization of Partially LBISTed Sequential Circuits. ETW'02: IEEE European Test Workshop, Corfou (Greece), France. pp.P nd., 2002. <lirmm-00269339>
  • Yves Bertrand, Marie-Lise Flottes, Florence Azaïs, Serge Bernard, Laurent Latorre, et al.. European Network for Test Education. DELTA'02: 1st International Workshop on Electronic DesignTest and Applications, Christchurch, New Zeland, pp.230-239, 2002. <lirmm-00268490>
  • Marie-Lise Flottes, J. Pouget, Bruno Rouzeyre. Power-Constrained Test Scheduling for SoCs Under a "No Session" Scheme. SoC Design Methodologies, Montpellier, France, Kluwer Academic Publishers, pp.401-412, 2002. <lirmm-00268504>
  • Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre. Software-Based Testing of Sequential VHDL Descriptions. ETW'03: IEEE European Test Workshop, Maastricht (The Netherlands), France. pp. 199-200, 2003. <lirmm-00269528>
  • Ziad Noun, Philippe Cauvet, Marie-Lise Flottes, Serge Bernard, David Andreu, et al.. Power Supply Investigation for Wireless Wafer Test. LATW'08: 9th Latin-American Test Workshop, Mar 2008, Puebla, Mexico. IEEE, pp.165-170, 2008. <lirmm-00260205>
  • Marie-Lise Flottes, Régis Poirier, Bruno Rouzeyre. A Simple and Effective Compression Scheme for Test Pins Reduction. HLDVT'02: IEEE International Workshop on High Level Design Validation and Test, Cannes (France), France. pp. 165-168, 2002. <lirmm-00269326>
  • Isabelle Vogel, Marie-Lise Flottes, Christian Landrault. Initialisatioin des Circuits Séquentiels Avant Test Intégré et Scan Partiel. Colloque du GDR CAO de Circuits et Systèmes Intégrés, Paris (France), France. pp. 39-42, 2002. <lirmm-00269335>
  • Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. A Reliable Architecture for the Advanced Encryption Standard. ETS: European Test Symposium, May 2008, Verbania, Italy. 13th IEEE European Test Symposium, pp.13-18, 2008. <lirmm-00285868>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An Integrated Validation Environment for Differential Power Analysis. IEEE Computer Society. DELTA'08: 4th IEEE International Symposium on Electronic Design, Test & Applications, Jan 2008, Hong Kong, pp.527-532, 2008, <http://www.ece.ust.hk/delta2008/>. <lirmm-00220458>
  • Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. L'auto-test d'un coeur de chiffrement AES. JNRDM'08 : Journées Nationales du Réseau Doctoral en Microélectronique, May 2008, France. pp.4, 2008, <http://www.u-bordeaux1.fr/jnrdm/>. <lirmm-00325878>
  • Erika Cota, Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Improving the Test of NoC-Based SoCs with Help of Compression Schemes. ISVLSI'08: IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France, IEEE Computer Society Publishing Services, pp.139-144, 2008, <http://www.lirmm.fr/isvlsi2008/>. <lirmm-00271574>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An Integrated Validation Environment for Differential Power Analysis. CryptArchi'08: Cryptographic Architectures Embedded in Reconfigurable Devices, Jun 2008, Tregastel, France. 2008. <lirmm-00332534>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Stuck-at-Faults Test using Differential Power Analysis. LPonTR'08: Workshop on Low Power Design Impact on Test and Reliability, May 2008, Italy. 2008, <http://www.cad.polito.it/~ets08/LPonTR/LPonTR.html>. <lirmm-00332529>
  • Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. AES-based BIST: Self-test, Test Pattern Generation and Signature Analysis. DELTA'08: 4th IEEE International Symposium on Electronic Design, Test & Applications, Jan 2008, Hong-Kong, IEEE, pp.314-321, 2008, <http://www.ece.ust.hk/delta2008/>. <lirmm-00258769>
  • Yves Bertrand, Marie-Lise Flottes, Florence Azaïs, Serge Bernard, Laurent Latorre, et al.. EuNICE-Test Project: A remote Access to Engineering Test for European Universities. EWME'02: European Workshop on MicroElectronics Education, University of Vigo, Spain, pp.133-136, 2002. <lirmm-00268489>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Novel Parity Bit Scheme for SBOX in AES Circuits. DDECS'07: Design and Diagnostics of Electronic Cicruits and Systems, Apr 2007, Cracovie, Pologne, IEEE, pp.267-271, 2007. <lirmm-00141799>
  • Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Marion Doulcier. Test and Security. CryptArchi'07: Cryptographic Architectures Embedded in Reconfigurable Devices, Jun 2007, Montpellier, France. 2007, <http://cryptarchi.univ-st-etienne.fr/workshop07/index.htm>. <lirmm-00163017>
  • Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. AES vs LFSR Based Test Pattern Generation: A Comparative Study. LATW'07: 8th IEEE Latin-American Test Workshop, Mar 2007, Cuzco, Peru, IEEE, pp.314-321, 2007. <lirmm-00138831>
  • Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Test Data Compression and TAM Design. IFIP VLSI-SOC 2007 - IFIP WG 10.5 International Conference on Very Large Scale Integration, Oct 2007, Atlanta, GA, USA, pp.178-183, 2007. <lirmm-00186171>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. On-Line Self-Test of AES Hardware Implementations. DSN'07: Workshop on Dependable and Secure Nanocomputing, Jun 2007, Edinburgh, United Kingdom. 2007. <lirmm-00163405>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. IEEE. IOLTS'07: 13th IEEE International On-Line Testing Symposium, Jul 2007, Heraklion, Crete, Greece, pp.57-62, 2007. <lirmm-00163244>
  • Marie-Lise Flottes, Marion Doulcier, Bruno Rouzeyre. Utilisation de ressources cryptographiques pour le test des circuits sécurisés. colloque du GDR SOC-SIP 2007, Jun 2007, Jussieu - Paris, France. 2007. <lirmm-00203332>
  • David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Secure Scan Design. DATE'06: Design, Automation and Test in Europe, Mar 2006, Munich, Germany, IEEE, pp.1177-1178, 2006. <lirmm-00132516>
  • David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. A Secure Scan Design Methodology. LATW'06: 7th IEEE Latin American Test Workshop, Mar 2006, Buenos Aires, Argentina. pp.81-86, 2006. <lirmm-00102752>
  • David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Secure Scan Techniques: a Comparison. IOLTS'06: 12th International On-Line Testing Symposium, Jul 2006, Como, Italy, IEEE, pp.119-124, 2006, <10.1109/IOLTS.2006.55>. <lirmm-00102857>
  • Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Compression de Données de Test : Réduction du Nombre de Broches et Gain en Temps de Test. JNRDM'06 : 9ièmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France. 2006. <lirmm-00102830>
  • David Hely, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Scan Pattern Watermarking. LATW'06: 7th IEEE Latin American Test Workshop, Mar 2006, Buenos Aires, pp.63-67, 2006. <lirmm-00102753>
  • Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Fitting ATE Channels with Scan Chains: A Comparison Between a Test Data Compression Technique and Serial Loading of Scan Chains. DELTA'06: Third IEEE International Workshop on Electronics DesignTest & Applications, Kuala Lumpur (Malaysia), IEEE, pp.295-300, 2006. <lirmm-00102704>
  • Serge Bernard, Marie-Lise Flottes, Philippe Cauvet, Hervé Fleury, Fabrice Verjus. Testing System-in-Package Wirelessly. LATW'06: 7th Latin American Test Workshop, 2006, Buenos Aires, Argentina. IEEE, pp.73-78, 2006. <lirmm-00102751>
  • Serge Bernard, David Andreu, Marie-Lise Flottes, Philippe Cauvet, Hervé Fleury, et al.. Testing System-In-Package Wirelessly. IEEE. DTIS'06: Design and Test of Integrated Systems in Nanoscale Tehnology, Sep 2006, Tunis (Tunisia), pp.222-226, 2006. <lirmm-00094916>
  • Laurent Latorre, Yves Bertrand, Michel Robert, Marie-Lise Flottes. Test Engineering Education in Europe: The EuNICE Test Project. EDUTECH'05, 2005, France. 2005. <lirmm-00106506>
  • Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre. Mutation sampling technique for the generation of structural test data. 6th IEEE Latin American Test Workshop, Mar 2005, Salvador, Bahia, Brazil. 2005. <hal-00378490>
  • David Hely, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Scan Design and Secure Chips : Can They Work Together. SAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia-Antipolis, France. 2005. <lirmm-00106546>
  • Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre. Mutation Sampling Technique for the Generation of Structural Test Data. DATE: Design, Automation and Test in Europe, 2005, Munich, Germany. IEEE, pp.1022, 2005. <lirmm-00105978>
  • David Hely, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Test Control for Secure Scan Designs. ETS: European Test Symposium, May 2005, Tallinn, Estonia. 10th IEEE European Test Symposium, pp.190-195, 2005. <lirmm-00106011>
  • Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre. Mutation Sampling Technique for the Generation of Structural Test Data. EDAA - European design and Automation Association. DATE: Design, Automation and Test in Europe, Mar 2005, Munich, Germany. 2, pp.1022-1023, 2005. <hal-00181680>
  • L. Krundel, S. Kumar Goel, E.J. Marinissen, Marie-Lise Flottes, Bruno Rouzeyre. User-Constrained Test Architecture Design for Modular SOC Testing. ETS: European Test Symposium, May 2004, Ajaccio, Corsica, France. 9th IEEE European Test Symposium, pp.80-85, 2004, <10.1109/ETSYM.2004.1347611>. <lirmm-00108903>
  • Marie-Lise Flottes. Testing a Secure Device: High Coverage with Very Low Observability. ITC'04: International Test Conference, Oct 2004, 2004. <lirmm-00109147>
  • Marie-Lise Flottes, Régis Poirier, Bruno Rouzeyre. On Using Test Vector Differences for Reducing Test Pin Numbers. DELTA'04: 2nd International Workshop on Electronic DesignTest and Applications, Jan 2004, Perth (Australia), IEEE Computer Society, pp.275-280, 2004. <lirmm-00108832>
  • Marie-Lise Flottes, Régis Poirier, Bruno Rouzeyre. An Arithmetic Structure for Test Data Horizontal Compression. DATE'04: DesignAutomation and Test in Europe, Feb 2004, Paris (France), pp.428-434, 2004. <lirmm-00108837>
  • David Hely, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Berard, et al.. Scan Design and Secure Chip. IOLTS'04: 10th International On-Line Testing Symposium, Jul 2004, Madeira Island, Portugal. IEEE, pp.219-224, 2004. <lirmm-00108909>
  • Laurent Latorre, Florence Azaïs, Marie-Lise Flottes, Serge Bernard, Régis Lorival, et al.. Test Digital, Test de Mémoires, Test Mixte : 5 Centres de Compétence pour la Formation en Europe. CNFM'04 : 8ème Journées Pédagogiques du Comité National de Formation en Microélectronique, 2004, Saint Malo, France. p. 242, 2004. <lirmm-00108671>
  • Marie-Lise Flottes, Yves Bertrand, L. Balado, E. Lupon, A. Biasizzo, et al.. Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competences in Europe. DELTA: Electronic Design, Test and Applications, Jan 2004, Perth, Australia. IEEE Computer Society, 2nd International Workshop on Electronic Design, Test and Applications, pp.135-139, 2004. <lirmm-00108831>
  • Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre. Software-Based Testing of Sequential VHDL Descriptions. ETW'03: IEEE European Test Workshop, Maastricht, Netherlands. pp.199-200, 2003. <lirmm-00269437>
  • Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre. Software-Based Testing of Sequential VHDL Descriptions. ETW'03: IEEE European Test Workshop, Maastricht, Netherlands. pp. 199-200, 2003. <lirmm-00191917>
  • Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes. Software-based testing of sequential vhdl descriptions. IEEE European Test Workshop, May 2003, Maastrich, France. pp.199-200, 2003. <hal-00193680>
  • Isabelle Vogel, Marie-Lise Flottes, Christian Landrault. Structural and Functional Analysis for Initialization of High Pipelined Industrial BISTed Circuits Using Partial Reset. LATW: 4th IEEE Latin American Test Workshop, Natal, Brazil. pp.84-89, 2003. <lirmm-00269462>
  • Julien Pouget, Erik Larsson, Zebo Peng, Marie-Lise Flottes, Bruno Rouzeyre. An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling. ETW: European Test Workshop, 2003, Maastricht, Netherlands. IEEE, pp.51-56, 2003. <lirmm-00191948>
  • Yves Bertrand, Marie-Lise Flottes, L. Balado, J. Figueras, A. Biasizzo, et al.. Test Engineering Education in Europe: The EuNICE-Test Project. IEEE Computer Society. MSE: Microelectronic Systems Education, Jun 2003, Anaheil, CA, United States. 2nd International Conference on Microelectronic Systems Education, pp.85-86, 2003, <10.1109/MSE.2003.1205266>. <lirmm-00269541>
  • Yves Bertrand, Marie-Lise Flottes, Florence Azaïs, Serge Bernard, Laurent Latorre, et al.. A Remote Access to Engineering Test Facilities for the Distant Education of European Microelectronics Students. FIE'02: Frontiers in Education Conference, Boston, Massachusetts (USA), pp.T2E-24, 2002. <lirmm-00191523>
  • Yves Bertrand, Marie-Lise Flottes, Florence Azaïs, Serge Bernard, Laurent Latorre, et al.. A Remote Access to Engineering Test Facilities for the Distant Education of European Microelectronics Students. FIE: Frontiers in Education, Nov 2002, Boston, Massachusetts, United States. pp.T2E-24, 2002. <lirmm-00269423>
  • Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre. A Heuristic for Test scheduling at System Level. DATE: Design Automation and Test in Europe, Mar 2002, Paris, France. pp.1124, 2002, <10.1109/DATE.2002.998480>. <lirmm-00268503>

Poster12 documents

  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Giorgio Di Natale, et al.. Design of Bulk Built-In Current Sensors to Detect Single Event Effects and Laser-Induced Fault Injection Attempts . Joint MEDIAN–TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands. <emse-01099040>
  • Rodolphe Giroudeau, Giorgio Di Natale, Marie-Lise Flottes, Florent Hernandez. Exact wafer matching process wafer to wafer inegration. Whorshop 3D integration Applications, France. pp.N/A, 2012. <lirmm-00805059>
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Calibrating Bulk Built-in Current Sensors for Detecting Transient Faults. Colloque GRD SoC-SiP, 2012, Lyon, France. 2012, Colloque National du Groupement de Recherche System-On-Chip et System-In-Package. <lirmm-00715126>
  • Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre. tLIFTING : A Multi-level Delay-annotated Fault Simulator for Digital Circuits. DCIS'2012: XVII Conference on Design of Circuits and Integrated Systems, Nov 2012, avignon, France. pp.1, 2012, <http://www.lirmm.fr/dcis2012/>. <lirmm-00799892>
  • Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Timing Issues of Transient Faults in Concurrent Error Detection Schemes. GdR SoC-SiP'2011: Colloque national du Groupement de Recherche System-On-Chip et System-In-Package, Lyon, France. http://www2.lirmm.fr/~w3mic/SOCSIP/, 2011, <http://www2.lirmm.fr/~w3mic/SOCSIP/>. <lirmm-00701798>
  • Philippe Cauvet, Olivier Potin, Marie-Lise Flottes, Serge Bernard, David Andreu, et al.. TOETS: Work Package 1. The European Nanoelectronics Forum 2011, Nov 2011, Dublin, Ireland. 2011, <http://www.catrene.org/web/forum2011/>. <lirmm-00653039>
  • Ziad Noun, Philippe Cauvet, Marie-Lise Flottes, David Andreu, Serge Bernard. Wireless Wafer Test for Iterative Testing During System Assembly. 3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Nov 2010, Austin, Texas, United States. 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, 2010, <http://www.ieee-tttc.org/ebshistory/2010/2010-06-14%203D-Test10%20CfP.html>. <lirmm-00537849>
  • Ziad Noun, Philippe Cauvet, Marie-Lise Flottes, David Andreu, Serge Bernard. Wireless Test Structure for Integrated Systems. ITC'2008: International Test Conference, Oct 2008, Santa Clara, CA, United States. pp.N/A, 2008, <10.1109/TEST.2008.4700704>. <lirmm-00375077>
  • Erika Cota, Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. Improving NoC-based Testing Through Compression Schemes. DATE: Design, Automation and Test in Europe, Apr 2007, Nice, France. 2007, <http://www.date-conference.com/conference/2007/prog/>. <lirmm-00170833>
  • Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre. TAM Design and Test Data Compression for SoC Test Cost Reduction. ETS: European Test Symposium, May 2007, Freiburg, Germany. 12th IEEE European Test Symposium, pp.241-246, 2007. <lirmm-00159044>
  • Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. A Dependable Parallel Architecture for SBoxes. ReCoSoc'07: International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2007, Montpellier, France. pp.CD-ROM, 2007. <lirmm-00163414>
  • Laurent Latorre, Yves Bertrand, Marie-Lise Flottes, Michel Robert. Test Engineering Education in Europe: The CRTC Experience Through the EuNICE-Test Project. Achim Rettberg and Christophe Bobda. IFIP TC10 Working Conference: EduTech'05, Oct 2005, France. pp.63-77, 2005, <http://www.springer.com/series/6102>. <lirmm-00106564>

Ouvrage (y compris édition critique et traduction)1 document

  • Florence Azaïs, Serge Bernard, Yves Bertrand, Marie-Lise Flottes, Patrick Girard, et al.. Test de Circuits et de Systèmes Intégrés. Collection EGEM, Ed.Hermès, 2004, 2-7462-0864-4. <lirmm-00109158>

Chapitre d'ouvrage5 documents

Brevet1 document

  • David Andreu, Philippe Cauvet, Marie-Lise Flottes, Ziad Noun, Serge Bernard. System and Method for Wirelessly Testing Integrated Circuits. Spain, Patent n° : EP 08290891 WO 2010031879 (A1). 2008, pp.N/A. <lirmm-00767777>

Autre publication23 documents

  • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Rapport Technique intermédiaire, Contrat TOETS CT 302, Programme CEE CATRENE. 2011. <lirmm-00679018>
  • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Rapport Technique de fin d'année, Contrat TOETS CT 302, Programme CEE CATRENE. 2011. <lirmm-00679022>
  • Patrick Girard, Serge Bernard, Florence Azaïs, Alberto Bosio, Luigi Dilillo, et al.. Contrat TOETS CT 302 - Programme CEE CATRENE (Rapport Intermédiaire). 2010. <lirmm-00504873>
  • Patrick Girard, Florence Azaïs, Serge Bernard, Alberto Bosio, Luigi Dilillo, et al.. TOETS CT302 - Programme CEE CATRENE - Summary Technical Report 2S-2009 - Rapport Technique de Fin d'année. 2010. <lirmm-00461745>
  • Patrick Girard, Serge Bernard, Alberto Bosio, Luigi Dilillo, Marie-Lise Flottes, et al.. Rapport Technique de fin de Contrat NanoTEST 2A702, Programme CEE MEDEA+. 2009. <lirmm-00406974>
  • Marion Doulcier, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Test and Harware Security. 2008. <lirmm-00365276>
  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702 - Programme CEE MEDEA - Rapport Technique de fin d'année. 2007. <lirmm-00199958>
  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702 - Programme CEE MEDEA - Rapport Technique intermédiaire. 2007. <lirmm-00199966>
  • Patrick Girard, Serge Bernard, Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702 - Programme CEE MEDEA+. 12927. 2006. <lirmm-00102699>
  • Patrick Girard, Serge Bernard, Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702, Programme CEE MEDEA+. 2006. <lirmm-00130758>
  • Patrick Girard, Serge Bernard, Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch, et al.. Contrat NanoTEST 2A702, Programme CEE MEDEA +. 2006. <lirmm-00130759>
  • Bruno Rouzeyre, Marie-Lise Flottes. Test Circuits Sécurisés 2. 11737. 2004, 2 p. <lirmm-00109182>
  • Patrick Girard, Michel Renovell, Serge Bernard, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Advanced Solutions for Innovative SOC Testing in Europe. 12702. 2004. <lirmm-00109190>
  • Marie-Lise Flottes, Yves Bertrand. Final Report, Contrat CEE, EuNICE-Test, IST-2000-30163. 11657. 2004. <lirmm-00109187>
  • Bruno Rouzeyre, Marie-Lise Flottes. Test Circuits Sécurisés 1. 11738. 2003, pp.3. <lirmm-00191973>
  • Bruno Rouzeyre, Marie-Lise Flottes. Test Circuits Sécurisés 1. 11738. 2003, 3 p. <lirmm-00269490>
  • Bruno Rouzeyre, Marie-Lise Flottes. Test Circuits Sécurisés 1. 11738. 2003, 3 p. <lirmm-00269804>
  • Patrick Girard, Michel Renovell, Florence Azaïs, Yves Bertrand, Marie-Lise Flottes, et al.. Advanced Solutions for Innovative SOC Testing in Europe, Contrat CEE ASSOCIATE A503, Programme MEDEA+ (Rapport Technique Intermédiaire). 10042. 2003, pp.P nd. <lirmm-00269720>
  • Patrick Girard, Michel Renovell, Florence Azaïs, Serge Bernard, Marie-Lise Flottes, et al.. Advanced Solutions for Innovative SOC Testing in Europe, Contrat CEE ASSOCIATE A503, Programme MEDEA+ (Rapport Technique de Fin d'Année). 10072. 2003, pp.P nd. <lirmm-00269749>
  • Yves Bertrand, Marie-Lise Flottes. Final Progress Report, Contrat CEE, EuNICE-Test, IST-2000-30163. 11477. 2003, pp.P nd. <lirmm-00269801>
  • Marie-Lise Flottes, Yves Bertrand. Intermediate Progress Report N° : OR2. 7717. 2002, pp.44. <lirmm-00268580>
  • Marie-Lise Flottes, Yves Bertrand, Florence Azaïs, Régis Lorival, Serge Bernard, et al.. Project Management and Trainer Education Deliverable: Management Report, Attendees and Training Contents, Training Evaluation. 8146. 2002. <lirmm-00268593>
  • Patrick Girard, Florence Azaïs, Serge Bernard, Yves Bertrand, Marie-Lise Flottes, et al.. Advanced Solutions for Innovative SOC Testing in Europe. 7724. 2002. <lirmm-00268586>

Rapport3 documents

  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat Nano TEST 2A702, Programme CEE MEDEA (Rapport Technique de fin d'année). 08026, 2008. <lirmm-00344408>
  • Patrick Girard, Serge Bernard, Alberto Bosio, Marie-Lise Flottes, Serge Pravossoudovitch, et al.. Contrat Nano TEST 2A702, Programme CEE MEDEA (Rapport Intermédiaire). 08027, 2008. <lirmm-00344415>
  • Nadia El Mrabet, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Jean-Claude Bajard. Differential Power Analysis against the Miller Algorithm. RR-08021, 2008. <lirmm-00323684>