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23

Marcello TRAIOLA, Ph.D.

In 2019, I earned a Ph.D. degree in Computer Engineering from the Montpellier University, in France. In 2016, I earned a Master’s degree in Computer Engineering - summa cum laude - from the Italian University “Federico II” of Naples, Italy. From Octobre 2019 to January 2020 I was in the USA at the semiconductor company MediaTek USA Inc., for an internship as R&D engineer. Since February 2020, I am at the Lyon Institute of Technology (École Centrale de Lyon), in France, as post-doctoral researcher. I actively research on emerging computing paradigms with focus on design, test and reliability.

 

Journal articles5 documents

  • Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio. A Survey of Testing Techniques for Approximate Integrated Circuits. Proceedings of the IEEE, Institute of Electrical and Electronics Engineers, In press, ⟨10.1109/JPROC.2020.2999613⟩. ⟨lirmm-02395609⟩
  • Marcello Traiola, Alessandro Savino, Stefano Di Carlo. Probabilistic estimation of the application-level impact of precision scaling in approximate computing applications. Microelectronics Reliability, Elsevier, 2019, 102, pp.#113309. ⟨10.1016/j.microrel.2019.06.002⟩. ⟨hal-03094543⟩
  • Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio. A Test Pattern Generation Technique for Approximate Circuits Based on an ILP-Formulated Pattern Selection Procedure. IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers, 2019, 18, pp.849-857. ⟨10.1109/TNANO.2019.2923040⟩. ⟨lirmm-02395306⟩
  • Lorena Anghel, Mounir Benabdenbi, Alberto Bosio, Marcello Traiola, Elena Ioana Vatajelu. Test and Reliability in Approximate Computing. Journal of Electronic Testing, Springer Verlag, 2018, 34 (4), pp.375-387. ⟨10.1007/s10836-018-5734-9⟩. ⟨hal-01961787⟩
  • Marcello Traiola, Mario Barbareschi, Alberto Bosio. Estimating dynamic power consumption for memristor-based CiM architecture. Microelectronics Reliability, Elsevier, 2018, 80, pp.241-248. ⟨10.1016/j.microrel.2017.12.009⟩. ⟨hal-03094521⟩

Conference papers17 documents

  • Riccardo Cantoro, Nikolaos Deligiannis, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea. Evaluating the Code Encryption Effects on Memory Fault Resilience. Latin American Test Symposium (LATS), Mar 2020, Maceio, Brazil. pp.1-6, ⟨10.1109/LATS49555.2020.9093670⟩. ⟨hal-03094594⟩
  • Riccardo Cantoro, Nikolaos Deligiannis, Matteo Sonza Reorda, Marcello Traiola, Emanuele Valea. Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network. International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2020, Frascati (on line), Italy. pp.1-4, ⟨10.1109/DFT50435.2020.9250869⟩. ⟨hal-03094602⟩
  • Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio. Maximizing Yield for Approximate Integrated Circuits. Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2020, Grenoble, France. pp.810-815, ⟨10.23919/DATE48585.2020.9116341⟩. ⟨lirmm-03036002⟩
  • Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sanchez, Alessandro Savino, et al.. Design, Verification, Test and In-Field Implications of Approximate Computing Systems. IEEE European Test Symposium (ETS), May 2020, Tallinn, Estonia. pp.1-10, ⟨10.1109/ETS48528.2020.9131557⟩. ⟨lirmm-03035724⟩
  • Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard. QAMR: an Approximation-Based FullyReliable TMR Alternative for Area Overhead Reduction. IEEE European Test Symposium (ETS), May 2020, Tallinn, Estonia. pp.1-6, ⟨10.1109/ETS48528.2020.9131574⟩. ⟨lirmm-03035640⟩
  • Marcello Traiola, Alessandro Savino, Mario Barbareschi, Stefano Di Carlo, Alberto Bosio. Predicting the Impact of Functional Approximation: from Component- to Application-Level. 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), Jul 2018, Platja d'Aro, Spain. pp.61-64, ⟨10.1109/IOLTS.2018.8474072⟩. ⟨hal-03094581⟩
  • Umberto Ferrandino, Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Petr Fišer‬, et al.. Synthesis of Finite State Machines on Memristor Crossbars. 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2018, Budapest, Hungary. pp.107-112, ⟨10.1109/DDECS.2018.000-3⟩. ⟨hal-03094575⟩
  • Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio. Testing Approximate Digital Circuits: Challenges and Opportunities. IEEE 19th Latin-American Test Symposium (LATS), Mar 2018, Sao Paulo, Brazil. pp.1-6, ⟨10.1109/LATW.2018.8349681⟩. ⟨lirmm-03033024⟩
  • Lukas Sekanina, Zdeněk Vašíček, Alberto Bosio, Marcello Traiola, Paolo Rech, et al.. Special session: How approximate computing impacts verification, test and reliability. 36th VLSI Test Symposium (VTS), Apr 2018, San Francisco, CA, United States. ⟨10.1109/VTS.2018.8368628⟩. ⟨lirmm-02421106⟩
  • Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio. On the Comparison of Different ATPG approaches for Approximate Integrated Circuits. 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Apr 2018, Budapest, Hungary. pp.85-90, ⟨10.1109/DDECS.2018.00022⟩. ⟨lirmm-03032856⟩
  • Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbarcschi, Alberto Bosio. Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits. 31st IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2018), Oct 2018, Chicago, United States. pp.1-6, ⟨10.1109/DFT.2018.8602939⟩. ⟨lirmm-02099895⟩
  • Marcello Traiola, Mario Barbareschi, Alberto Bosio. Formal Design Space Exploration for memristor-based crossbar architecture. 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Apr 2017, Dresden, Germany. pp.145-150, ⟨10.1109/DDECS.2017.7934557⟩. ⟨hal-03094567⟩
  • Mario Barbareschi, Alberto Bosio, Hoang Anh Du Nguyen, Said Hamdioui, Marcello Traiola, et al.. Memristive devices: Technology, Design Automation and Computing Frontiers. DTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2017, Palma de Mallorca, Spain. ⟨10.1109/DTIS.2017.7930178⟩. ⟨hal-01525719⟩
  • Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio. Towards digital circuit approximation by exploiting fault simulation. EWDTS: East-West Design & Test Symposium, Sep 2017, Novi Sad, Serbia. ⟨10.1109/EWDTS.2017.8110108⟩. ⟨lirmm-01718583⟩
  • Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, et al.. Towards approximation during test of Integrated Circuits. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2017, Dresden, Germany. ⟨10.1109/DDECS.2017.7934574⟩. ⟨lirmm-01718580⟩
  • Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, et al.. Can we Approximate the Test of Integrated Circuits?. WAPCO: Workshop On Approximate Computing, Jan 2017, Stockholm, Sweden. ⟨lirmm-02004418⟩
  • Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Alberto Bosio. XbarGen: A memristor based boolean logic synthesis tool. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Sep 2016, Tallinn, Estonia. ⟨10.1109/VLSI-SoC.2016.7753567⟩. ⟨hal-03094562⟩

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