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LD
Luigi Dilillo
100
Documents
Identifiants chercheurs
luigi-dilillo- IdRef : 18891885X
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0000-0002-1295-2688
Présentation
Publications
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An ATPG Flow to Generate Crosstalk-Aware Path Delay PatternISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.515-520, ⟨10.1109/ISVLSI.2015.99⟩
Communication dans un congrès
lirmm-01272933v1
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A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply NoiseISVLSI: International Symposium on Very Large Scale Integration, Jul 2014, Tampa, FL, United States. pp.226-231, ⟨10.1109/ISVLSI.2014.42⟩
Communication dans un congrès
lirmm-01248592v1
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Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounceDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. pp.207-212, ⟨10.1109/DDECS.2014.6868791⟩
Communication dans un congrès
lirmm-01248599v1
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Real-Time Testing of 90nm COTS SRAMs at Concordia Station in AntarcticaNSREC: Nuclear and Space Radiation Effects Conference, Jul 2014, Paris, France
Communication dans un congrès
lirmm-01237709v1
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SEU Monitoring in Mixed-Field Radiation Environments of Particle AcceleratorsRADECS: Radiation and Its Effects on Components and Systems, Sep 2013, Oxford, United Kingdom. pp.1-4, ⟨10.1109/RADECS.2013.6937419⟩
Communication dans un congrès
lirmm-00839085v1
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Worst-Case Power Supply Noise and Temperature Distribution Analysis for 3D PDNs with Multiple Clock DomainsNEWCAS: New Circuits and Systems, Jun 2013, Paris, France. ⟨10.1109/NEWCAS.2013.6573628⟩
Communication dans un congrès
lirmm-00839042v1
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Characterization of an SRAM Based Particle Detector For Mixed-Field Radiation EnvironmentsIWASI: International Workshop on Advances in Sensors and Interfaces, Jun 2013, Bari, Italy. pp.75-80, ⟨10.1109/IWASI.2013.6576070⟩
Communication dans un congrès
lirmm-00839046v1
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On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cellDFT: Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2013, New York, United States. pp.143-148, ⟨10.1109/DFT.2013.6653597⟩
Communication dans un congrès
lirmm-01238413v1
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Evaluating An SEU Monitor For Mixed-Field Radiation EnvironmentsiWoRID: International Workshop on Radiation Imaging Detectors, SOLEIL Synchrotron, Jun 2013, Paris, France
Communication dans un congrès
lirmm-01238433v1
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SRAM Soft Error Rate Evaluation Under Atmospheric Neutron Radiation and PVT variationsIOLTS: International On-Line Testing Symposium, Jul 2013, Chania, Crete, Greece. pp.145-150, ⟨10.1109/IOLTS.2013.6604066⟩
Communication dans un congrès
lirmm-00818955v1
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Multiple-Cell-Upsets on a commercial 90nm SRAM in Dynamic ModeRADECS: Radiation and Its Effects on Components and Systems, Sep 2013, Oxford, United Kingdom. pp.1-4, ⟨10.1109/RADECS.2013.6937429⟩
Communication dans un congrès
lirmm-00839062v1
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Temperature Impact on the Neutron SER of a Commercial 90nm SRAMNSREC: Nuclear and Space Radiation Effects Conference, Jul 2013, San Francisco, Ca, United States. pp.1-4
Communication dans un congrès
lirmm-00805291v1
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Robustness Improvement of Digital Circuits A New Hybrid Fault Tolerant ArchitectureJNRDM'11: Journées Nationales du Réseau Doctoral de Microélectronique, Paris, France
Communication dans un congrès
lirmm-00679509v1
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A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital CircuitsGDR SOC-SIP'11 : Colloque GDR SoC-SiP, Lyon, France
Communication dans un congrès
lirmm-00679513v1
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Radiation Induced Effects on Electronic Systems and ICsSETS: South European Test Seminar, Mar 2012, Sauze d'Oulx, Italy
Communication dans un congrès
lirmm-00807055v1
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Advanced Test Methods for SRAMsVTS: VLSI Test Symposium, Apr 2012, Hyatt Maui, HI, United States. pp.300-301, ⟨10.1109/VTS.2012.6231070⟩
Communication dans un congrès
lirmm-00805049v1
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Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line CouplingGDR SOC-SIP'11 : Colloque GDR SoC-SiP, Lyon, France
Communication dans un congrès
lirmm-00679522v1
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Test and Reliability of Magnetic Random Access MemoriesGDR SOC-SIP'11: Colloque GDR SoC-SiP, Lyon, France
Communication dans un congrès
lirmm-00679516v1
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Mapping Test Power to Functional Power through Smart X-Filling for LOS SchemeLPonTR'11: IEEE International Workshop on the Impact of Low Power on Test and Reliability, Trondheim, Norway
Communication dans un congrès
lirmm-00651905v1
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Error Resilient Infrastructure for Data Transfer in a Distributed Neutron DetectorDFT 2011 - International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2011, Vancouver, Canada. pp.294-301, ⟨10.1109/DFT.2011.41⟩
Communication dans un congrès
lirmm-00651226v1
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Test Relaxation and X-filling to Reduce Peak Power During At-Speed LOS TestingGDR SOC-SIP'10 : Colloque GDR SoC-SiP, Cergy, France
Communication dans un congrès
lirmm-00553989v1
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Detecting NBTI Induced Failures in SRAM Core-CellsVTS'10: VLSI Test Symposium, Santa Cruz, CA, United States. pp.75-80
Communication dans un congrès
lirmm-00553612v1
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Failure Analysis and Test Solutions for Low-Power SRAMsATS: Asian Test Symposium, Nov 2011, New Delhi, India. pp.459-460, ⟨10.1109/ATS.2011.97⟩
Communication dans un congrès
lirmm-00805123v1
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Robust Structure for Data Collection and Transfer in a Distributed SRAM Based Neutron Test BenchWorkshop on Dependability Issues in Deep-Submicron Technologies, Trondheim, Norway
Communication dans un congrès
lirmm-00651796v1
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Simultaneous Power and Thermal Integrity Analysis for 3D Integrated SystemsLPonTR'11: IEEE International Workshop on the Impact of Low Power on Test and Reliability, Trondheim, Norway
Communication dans un congrès
lirmm-00651802v1
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Optimized March Test Flow for Detecting Memory Faults in SRAM Devices Under Bit Line CouplingDDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Netherlands. pp.353-358
Communication dans un congrès
lirmm-00592182v1
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Power Supply Noise and Ground Bounce Aware Pattern Generation for Delay TestingNEWCAS: International New Circuits and Systems Conference, Jun 2011, Bordeaux, France. pp.73-76, ⟨10.1109/NEWCAS.2011.5981222⟩
Communication dans un congrès
lirmm-00647815v1
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A Study of Path Delay Variations in the Presence of Uncorrelated Power and Ground Supply NoiseDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2011, Cottbus, Germany. pp.189-194, ⟨10.1109/DDECS.2011.5783078⟩
Communication dans un congrès
lirmm-00592000v1
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On Using Address Scrambling to Implement Defect Tolerance in SRAMsITC'2011: International Test Conference, Sep 2011, Anaheim, CA, United States. pp.N/A
Communication dans un congrès
lirmm-00647773v1
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A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital CircuitsATS 2011 - 20th IEEE Asian Test Symposium, Nov 2011, New Delhi, India. pp.136-141, ⟨10.1109/ATS.2011.89⟩
Communication dans un congrès
lirmm-00651238v1
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On Using Address Scrambling for Defect Tolerance in SRAMsInternational test Conference, Sep 2011, Anaheim, CA, United States. pp.1-8, ⟨10.1109/TEST.2011.6139149⟩
Communication dans un congrès
lirmm-00805334v1
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A DfT Solution for Oxide Thickness Varitions in ATMEL eFlash TechnologyDTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2011, Athènes, Greece
Communication dans un congrès
lirmm-00647750v1
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Variability Analysis of an SRAM Test ChipETS: European Test Symposium, May 2011, Trondheim, Norway
Communication dans un congrès
lirmm-00651791v1
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On using a SPICE-like TSTAC™ eFlash model for design and testDDECS: Design and Diagnostics of Electronic Circuits ans Systems, Apr 2011, Cottbus, Germany. pp.359-370, ⟨10.1109/DDECS.2011.5783111⟩
Communication dans un congrès
lirmm-00592203v1
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Power Reduction Through X-filling of Transition Fault Test Vectors for LOS TestingDTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2011, Athènes, Greece. ⟨10.1109/DTIS.2011.5941434⟩
Communication dans un congrès
lirmm-00647760v1
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A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay TestingETS 2011 - 16th IEEE European Test Symposium, May 2011, Trondheim, Norway. pp.153-158, ⟨10.1109/ETS.2011.21⟩
Communication dans un congrès
lirmm-00647822v1
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Analyse et modélisation des défauts résistifs affectant les mémoires FlashGDR SOC-SIP'10 : Colloque GDR SoC-SiP, Cergy, France
Communication dans un congrès
lirmm-00553947v1
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Analysis and Fault Modeling of Actual Resistive Defects in Flash MemoriesJNRDM'10 : Journées Nationales du Réseau Doctoral de Microélectronique, Montpellier, France
Communication dans un congrès
lirmm-00553935v1
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Tolérance aux fautes et rendement de fabricationGDR SOC-SIP'10 : Colloque GDR SoC-SiP, Cergy, France
Communication dans un congrès
lirmm-00553995v1
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Impact of Resistive-Bridging Defects in SRAM Core-CellDELTA'10: International Symposium on Electronic Design, Test & Applications, Ho Chi Minh, Vietnam. pp.265-270
Communication dans un congrès
lirmm-00553592v1
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A Comprehensive System-on-Chip Logic DiagnosisATS: Asian Test Symposium, 2010, Shanghai, China. pp.237-242
Communication dans un congrès
lirmm-00545131v1
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A Statistical Simulation Method for Reliability Analysis of SRAM Core-CellsDAC: Design Automation Conference, Jun 2010, Anaheim, United States. pp.853-856
Communication dans un congrès
lirmm-00553619v1
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Setting Test Conditions for Detecting Faults Induced by Random Dopant Fluctuation in SRAM Core-CellsVARI: Workshop on CMOS Variability, 2010, Montpellier, France
Communication dans un congrès
lirmm-00553626v1
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Setting Test Conditions for Improving SRAM ReliabilityETS: European Test Symposium, May 2010, Prague, Czech Republic. pp.257-262
Communication dans un congrès
lirmm-00492741v1
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Analysis of Power Consumption and Transition Fault Coverage for LOS and LOC Testing SchemesDDECS'10: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2010, Vienna, Austria. pp.376-381
Communication dans un congrès
lirmm-00475734v1
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A Memory Fault Simulator for Radiation-Induced Effects in SRAMsATS: Asian Test Symposium, 2010, Shanghai, China. pp.100-105
Communication dans un congrès
lirmm-00545102v1
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Analysis of Resistive-Bridging Defects in SRAM Core-Cells: a Comparative Study from 90nm down to 40nm Technology NodesETS: European Test Symposium, May 2010, Prague, Czech Republic. pp.132-137
Communication dans un congrès
lirmm-00493236v1
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A Two-Layer SPICE Model of the ATMEL TSTAC eFlash Memory Technology for Defect Injection and Faulty Behavior PredictionETS: European Test Symposium, May 2010, Prague, Czech Republic. pp.81-86
Communication dans un congrès
lirmm-00493204v1
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Power Reduction Through X-filling of Transition Fault Test Vectors for LOS TestingLPonTR:
Impact of Low-Power design on Test and Reliability, May 2010, Prague, Czech Republic
Communication dans un congrès
lirmm-00553930v1
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Using TMR Architectures for SoC Yield ImprovementVALID'09: The First International Conference on Advances in System Testing and Validation Lifecycle, 2009, Porto, Portugal. pp.155-160
Communication dans un congrès
lirmm-00406967v1
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Delay Fault Diagnosis in Sequential CircuitsATS: Asian Test Symposium, Nov 2009, Taichung, Taiwan. pp.355-360
Communication dans un congrès
lirmm-00406968v1
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Comprehensive Bridging Fault Diagnosis based on the SLAT ParadigmDDECS'09: 12th IEEE Symposium on Design and Diagnostics of Electronic Systems, pp.264-269
Communication dans un congrès
lirmm-00371198v1
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Trade-off Between Power Dissipation and Delay Fault Coverage For LOS and LOC Testing SchemesImpact of Low-Power Design on Test and Reliability, Spain
Communication dans un congrès
lirmm-00435005v1
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A New Design-for-Test Technique for SRAM Core-Cell Stability FaultsDATE: Design, Automation and Test in Europe, Apr 2009, Nice, France. pp.1344-1348, ⟨10.1109/DATE.2009.5090873⟩
Communication dans un congrès
lirmm-00371374v1
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A Fault-Simulation-Based Approach for Logic DiagnosisDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Apr 2009, Cairo, Egypt. pp.216-221
Communication dans un congrès
lirmm-00371377v1
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A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMsITC'2008: International Test Conference, Oct 2008, Santa Clara, CA, United States. pp.1-10, ⟨10.1109/TEST.2008.4700555⟩
Communication dans un congrès
lirmm-00341798v1
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Impact of Technology Scaling on Defects and Parameter Deviations in Embedded SRAMsVLSI Test Symposium, Apr 2008, San Diego, California, United States. pp.336
Communication dans un congrès
lirmm-00324151v1
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A Signature-based Approach for Diagnosis of Dynamic Faults in SRAMsDTIS: Design and Technology of Integrated Systems in Nanoscale Era, Mar 2008, Tunis, Tunisia. pp.001-006, ⟨10.1109/DTIS.2008.4540243⟩
Communication dans un congrès
lirmm-00324143v1
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A History-Based Technique for Faults Diagnosis in SRAMsColloque GDR SoC-SiP, France
Communication dans un congrès
lirmm-00341821v1
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March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge CircuitDDECS'06: Design and Diagnostics of Electronic Circuits and Systems, Apr 2006, Prague, République Tchèque, pp.256-261
Communication dans un congrès
lirmm-00134776v1
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Resistive-Open Defect Injection in SRAM Core-Cell: Analysis and Comparison Between 0.13 um and 90 nm TechnologiesDAC: Design Automation Conference, Jun 2005, Anaheim, CA, United States. pp.857-862
Communication dans un congrès
lirmm-00136906v1
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Incidence des Défauts Résistifs dans les Circuits de Précharge des Mémoires SRAMJNRDM 2005 - 8e Journées Nationales du Réseau Doctoral de Microélectronique, May 2005, Paris, France
Communication dans un congrès
lirmm-00106529v1
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Resistive-Open Defect Injection in SRAM Core-Cell: Analysis and Comparison between 0.13μm and 90nm TechnologiesDAC: Design Automation Conference, May 2005, Anaheim, CA, United States. pp.857-862, ⟨10.1145/1065579.1065804⟩
Communication dans un congrès
lirmm-00106558v1
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Data Retention Fault in SRAM Memories: Analysis and Detection ProceduresVTS 2005 - 23rd IEEE VLSI Test Symposium, May 2005, Palm Springs, CA, United States. pp.183-188, ⟨10.1109/VTS.2005.37⟩
Communication dans un congrès
lirmm-00105995v1
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Resistive-Open Defect Influence in SRAM Pre-Charge Circuits: Analysis and CharacterizationETS: European Test Symposium, May 2005, Tallinn, Estonia. pp.116-121, ⟨10.1109/ETS.2005.33⟩
Communication dans un congrès
lirmm-00106010v1
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Efficient Test of Dynamic Read Destructive Faults in SRAM MemoriesLATW: Latin American Test Workshop, Mar 2005, Salvador, Bahia, Brazil. pp.40-45
Communication dans un congrès
lirmm-00106515v1
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Dynamic Read Destructive Faults in Embedded-SRAMs: Analysis and March Test SolutionETS: European Test Symposium, May 2004, Ajaccio, Corsica, France. pp.140-145
Communication dans un congrès
lirmm-00108795v1
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Test March pour la Détection des Fautes Dynamiques dans les Décodeurs de Mémoires SRAMJNRDM'04 : 7ièmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2004, Marseille, France. pp.495-497
Communication dans un congrès
lirmm-00108644v1
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March iC-: An Improved Version of March C- for ADOFs DetectionVTS: VLSI Test Symposium, Apr 2004, Napa Valley, CA, United States. pp.129-134, ⟨10.1109/VTEST.2004.1299236⟩
Communication dans un congrès
lirmm-00108772v1
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Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test SolutionATS: Asian Test Symposium, Nov 2004, Kenting, Taiwan. pp.266-271
Communication dans un congrès
lirmm-00108800v1
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March Tests Improvements for Address Decoder Open and Resistive Open Fault DetectionLATW: Latin American Test Workshop, Mar 2004, Cartagena, Colombia. pp.31-36
Communication dans un congrès
lirmm-00108642v1
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Comparison of open and resistive-open defect test conditions in SRAM address decodersATS: Asian Test Symposium, Nov 2003, Xian, China. pp.250-255, ⟨10.1109/ATS.2003.1250818⟩
Communication dans un congrès
lirmm-01238821v1
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Investigating Multiple-Cell-Upsets on a 90mn SRAMColloque GDR SoC-SiP, 2013, Lyon, France. 2013
Poster de conférence
lirmm-00839108v1
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Is Test Power Reduction Through X-Filling Good Enough?ITC'2010: International Test Conference, Nov 2010, Austin, Texas, United States. 2010
Poster de conférence
lirmm-00537926v1
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Parity Prediction Synthesis for Nano-Electronic Gate DesignsITC'2010: International Test Conference, Nov 2010, Austin, Texas, United States. pp.N/A, 2010
Poster de conférence
lirmm-00537938v1
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Analysis of Resistive-Bridging Defects in SRAM Core-Cell: Impact within the Core-Cell and in the Memory ArrayETS: European Test Symposium, May 2009, Sevilla, Spain. 14th IEEE European Test Symposium, 2009
Poster de conférence
lirmm-00433796v1
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SoC Yield Improvement for Future Nanoscale TechnologiesETS 2009 - 14th IEEE European Test Symposium | PhD Forum, May 2009, Sevilla, Spain. 2009
Poster de conférence
lirmm-00433798v1
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A Logic Diagnosis Approach for Sequential CircuitsPoster de conférence lirmm-00433792v1 |
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Test des Mémoires FLASH NANDColloque GDR SoC-SiP, France. 2009
Poster de conférence
lirmm-00433770v1
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SRAM Core-cell Quality MetricsGDR SOC SIP, France. 2009
Poster de conférence
lirmm-00434962v1
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Trade-off Between Power Dissipation and Delay Fault Coverage for LOS and LOC Testing SchemesGDR SOC SIP, France. 2009
Poster de conférence
lirmm-00434959v1
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NAND Flash Testing: A Preliminary Study on Actual DefectsITC: International Test Conference, Nov 2009, Austin, TX, United States. 2009, ⟨10.1109/TEST.2009.5355898⟩
Poster de conférence
lirmm-00433765v1
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Advanced Test Methods for SRAMs - Effective Solutions for Dynamic Fault Detection in Nanoscaled TechnologiesSpringer, 171 p., 2009, 978-1-4419-0937-4
Ouvrages
lirmm-00371359v1
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TOETS CT302 - Programme CEE CATRENE - Summary Technical Report 2S-2009 - Rapport Technique de Fin d'année2010
Autre publication scientifique
lirmm-00461745v1
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Rapport Technique de fin de Contrat NanoTEST 2A702, Programme CEE MEDEA+2009
Autre publication scientifique
lirmm-00406974v1
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