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	Analysis and Fault Modeling of Actual Resistive Defects in ATMELtm eFlash Memories Pierre-Didier Mauroux , Arnaud Virazel , Alberto Bosio , Luigi Dilillo , Patrick Girard Journal of Electronic Testing: : Theory and Applications, 2012, 28 (2), pp.215-228. ⟨10.1007/s10836-012-5277-4⟩ Article dans une revue lirmm-00806773v1

	A DfT Solution for Oxide Thickness Varitions in ATMEL eFlash Technology Pierre-Didier Mauroux , Arnaud Virazel , Alberto Bosio , Luigi Dilillo , Patrick Girard DTIS: Design and Technology of Integrated Systems in Nanoscale Era, 2011, Athènes, Greece Communication dans un congrès lirmm-00647750v1
	On using a SPICE-like TSTAC™ eFlash model for design and test Pierre-Didier Mauroux , Arnaud Virazel , Alberto Bosio , Luigi Dilillo , Patrick Girard DDECS: Design and Diagnostics of Electronic Circuits ans Systems, Apr 2011, Cottbus, Germany. pp.359-370, ⟨10.1109/DDECS.2011.5783111⟩ Communication dans un congrès lirmm-00592203v1
	Analyse et modélisation des défauts résistifs affectant les mémoires Flash Pierre-Didier Mauroux , Arnaud Virazel , Alberto Bosio , Luigi Dilillo , Patrick Girard GDR SOC-SIP'10 : Colloque GDR SoC-SiP, Cergy, France Communication dans un congrès lirmm-00553947v1
	A Two-Layer SPICE Model of the ATMEL TSTAC eFlash Memory Technology for Defect Injection and Faulty Behavior Prediction Pierre-Didier Mauroux , Arnaud Virazel , Alberto Bosio , Luigi Dilillo , Patrick Girard ETS: European Test Symposium, May 2010, Prague, Czech Republic. pp.81-86 Communication dans un congrès lirmm-00493204v1

	NAND Flash Testing: A Preliminary Study on Actual Defects Pierre-Didier Mauroux , Arnaud Virazel , Alberto Bosio , Luigi Dilillo , Patrick Girard ITC: International Test Conference, Nov 2009, Austin, TX, United States. 2009, ⟨10.1109/TEST.2009.5355898⟩ Poster de conférence lirmm-00433765v1

Luigi Dilillo