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200 résultats
Method to increase the switching speed of MOS transistors by dynamic bias of the bulk1995-International-Semiconductor-Conference.-CAS'95-Proceedings-Cat.-No.95TH8071, 1995, Sinaia, France. pp.241-4, ⟨10.1109/SMICND.1995.494907⟩
Communication dans un congrès
hal-00015787v1
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On the Dependability of 3D InterconnectsEcole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'12), Jan 2012, Alpes d'Huez, France
Communication dans un congrès
hal-00677047v1
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Dependable Multicore Architectures at Nanoscale: The View From EuropeIEEE Design & Test, 2015, 32 (2), pp.17-28. ⟨10.1109/MDAT.2014.2359572⟩
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hal-01334167v1
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Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic DevicesNANOARCH '22: 17th ACM International Symposium on Nanoscale Architectures, Dec 2022, Virtual OR USA, United States. pp.1-6, ⟨10.1145/3565478.3572536⟩
Communication dans un congrès
hal-04149770v1
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Design-time exploration for process, environment and aging compensation techniques for low power reliable-Aware designIEEE Transactions on Emerging Topics in Computing, 2022, 10 (2), pp.581-590. ⟨10.1109/TETC.2021.3136288⟩
Article dans une revue
hal-03599345v1
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Managing Aging Induced Reliability at Run-time7th Workshop on Cross-layer Resiliency (IWCR'2019), Jul 2019, Stuttgart, Germany
Communication dans un congrès
hal-02457526v1
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Neuromorphic CircuitsL’Intelligence Naturelle au cœur des enjeux de l’Intelligence Artificielle – Les atouts du site grenoblois, Jul 2018, Grenoble, France
Communication dans un congrès
hal-02473890v1
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Asynchronous Current Monitors for Transient Fault Detection in Deep Submicron CMOS4th IEEE International On-Line Testing Workshop (IOLTW'98), Jul 1998, Capri, Italy
Communication dans un congrès
hal-01413136v1
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Application-independent testing of multilevel interconnect in mesh-based FPGAsIEEE 10th International Conference on Design and Technologies for Integrated System in Nanoscale (DTIS'15), Apr 2015, Naples, Italy. pp.1-6
Communication dans un congrès
hal-01400596v1
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Designing Single Chip Massively Parallel Processors Affected by Extreme Failure RatesDesign, Automation & Test in Europe Conference & Exhibition (DATE'12), Mar 2012, Dresden, Germany
Communication dans un congrès
hal-01408773v1
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On the Dependability of 3D InterconnectsDependability Issues in Deep-submicron Technologies Workshop (DDT'11), May 2011, Trondheim, Norway
Communication dans un congrès
hal-00650195v1
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Checkpoint and rollback recovery in network-on-chip based systemsStudent forum at 15th Asia and South Pacific Design Automation Conference (ASP-DAC'10), Jan 2010, Taipei, Taiwan
Communication dans un congrès
hal-00505319v1
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Resistance Increase Due to Electromigration Induced Depletion Under TSVIEEE International Reliability Physics Symposium (IRPS'11), Monterey, CA, USA, April 10-14, Apr 2011, Monterey, ca., United States. pp.3F.4.1 - 3F.4.6, ⟨10.1109/IRPS.2011.5784499⟩
Communication dans un congrès
hal-00599391v1
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Transient and permanent fault tolerance memory cells for unreliable future nanotechnologiesIEEE Latin American Test Workshop (LATW'05), Mar 2005, Salvador Bahia, Brazil. pp.187-192
Communication dans un congrès
hal-00457112v1
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Efficient Fault-Tolerant Adaptive Routing under an unconstrained Set of Node and Link Failures for Many Cores System On ChipWorkshop on Dependable Multicore and Transactional Memory Systems (DMTM'14), (joint to HIPEAC event), Jan 2014, Vienna, Austria. pp.1-2
Communication dans un congrès
hal-01128367v1
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Improving the Scalability of Checkpoint Recovery for Networks-on-ChipIEEE International Symposium on Circuits and Systems (ISCAS'08), Seattle, May 2008, Washington, United States. pp.2793-2796, ⟨10.1109/ISCAS.2008.4542037⟩
Communication dans un congrès
hal-00378206v1
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A Transistor Placement Technique Using Genetic Algorithm And Analytical ProgrammingVLSI-SOC: From Systems to Silicon, (selected contributions from VLSI-SoC'05), Springer, pp.331-344, Vol.240, 2007, Series: IFIP International Federation for Information Processing, ⟨10.1007/978-0-387-73661-7_21⟩
Chapitre d'ouvrage
hal-00191996v1
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A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies22nd IEEE VLSI Test Symposium, 2004, Napa Valley, United States. pp.313, ⟨10.1109/VTEST.2004.1299258⟩
Communication dans un congrès
hal-00005750v1
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Configurable Serial Fault-Tolerant Link for Communication in 3D Integrated SystemsInternational On-Line Test Symposium (IOLTS'10), Jul 2010, Corfu, Greece. pp.115-120
Communication dans un congrès
hal-00505276v1
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Reliability approach of high density Through Silicon Via (TSV)12th Electronics Packaging Technology Conference (EPTC'10), Dec 2010, Singapore, Singapore. pp.321 - 324, ⟨10.1109/EPTC.2010.5702655⟩
Communication dans un congrès
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Backpropagation-based learning techniques for deep spiking neural networks: a surveyIEEE Transactions on Neural Networks and Learning Systems, 2023, pp.1-16. ⟨10.1109/TNNLS.2023.3263008⟩
Article dans une revue
hal-04064177v1
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Spin Orbit Torque-based Crossbar Array for Error Resilient Binary Convolutional Neural Network23RD IEEE LATIN-AMERICAN TEST SYMPOSIUM, Sep 2022, Montevideo, Uruguay
Communication dans un congrès
hal-03834907v1
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Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault ToleranceIEEE Transactions on Nanotechnology, 2020, pp.39-53. ⟨10.1109/TNANO.2020.3044017⟩
Article dans une revue
hal-03065940v1
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Early system failure prediction by using aging in situ monitors: Methodology of implementation and application resultsIEEE 34th VLSI Test Symposium (VTS'16), Apr 2016, Las Vegas, NE, United States
Communication dans un congrès
hal-01357213v1
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An Analysis and Design Technique to Reduce SET Sensitivity in Combinational Integrated Circuits16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-Soc'08), Oct 2008, Rhodes Island, Greece. pp.114-117
Communication dans un congrès
hal-01408783v1
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I-BIRAS: « Interconnect Built-In Self-Repair and Adaptive-SerializationInternational Test Conference Workshop on Test of 3D Stacked Systems (3D-TEST), Nov 2010, Austin, TX, United States
Communication dans un congrès
hal-01408780v1
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From 1.8V to 0.19V voltage bias on analog spiking neuron in 28nm UTBB FD-SOI technologyEUROSOI-ULIS 2020, Sep 2020, Caen, France
Communication dans un congrès
hal-03001733v1
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Robustness of Timing in-situ Monitors for AVS ManagementIEEE International Reliability Physics Semiconductor (IRPS'16), Apr 2016, Passadena, United States
Communication dans un congrès
hal-01474794v1
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Moniteurs de fiabilité embarqués en technologie FDSOI: Implémentation et ApplicationsEcole d'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes (FETCH'16), Jan 2016, Vilard de Lans, France
Communication dans un congrès
hal-01474809v1
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Electromigration Behavior of 3D-IC TSVSecond IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D IC), in conjuction with ITC, Sep 2011, Anaheim, United States
Communication dans un congrès
hal-00651930v1
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