Number of documents

35

Publications


Journal articles4 documents

  • Laurent Sauvage, Tarik Graba, Thibault Porteboeuf. Multi-Level Formal Analysis, A New Direction for Fault Injection Attack?. Journal of Cryptographic Engineering, 2016. ⟨hal-02287457⟩
  • Christophe Clavier, Guillaume Duc, Jean-Luc Danger, Moulay Aziz Elaabid, Benoît Gérard, et al.. Practical Improvements of Side-Channel Attacks on AES: Feedback from the 2nd DPA Contest. Journal of Cryptographic Engineering, 2014, 4 (4), pp.259-274. ⟨10.1007/s13389-014-0075-9⟩. ⟨hal-02286726⟩
  • Laurent Sauvage, Jean-Luc Danger, Sylvain Guilley, Naofumi Homma, Yu-Ichi Hayashi. Advanced Analysis of Faults Injected Through Conducted Intentional ElectroMagnetic Interferences. Transactions on Electromagnetic Compatibility, 2013. ⟨hal-02286327⟩
  • Yu-Ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, et al.. Analysis of Electromagnetic Information Leakage from Cryptographic Devices with Different Physical Structures. IEEE Transactions on Electromagnetic Compatibility, 2013, 55 (3), pp.571-580. ⟨hal-02286819⟩

Conference papers26 documents

  • Oualid Trabelsi, Laurent Sauvage, Jean-Luc Danger. Impact of Intentional Electromagnetic Interference on Pure Combinational Logic. 2019 International Symposium on Electromagnetic Compatibility - EMC EUROPE, Sep 2019, Barcelone, Spain. pp.398-403. ⟨hal-02318731⟩
  • Shugo Kaji, Masahiro Kinugawa, Daisuke Fujimoto, Laurent Sauvage, Jean-Luc Danger, et al.. Method for Identifying Individual Electronic Devices Focusing on Differences in Spectrum Emissions. 2019 Joint International Symposium on Electromagnetic Compatibility and Asia-Pacific International Symposium on Electromagnetic Compatibility, Sep 2019, Sapporo, Japan. ⟨hal-02319485⟩
  • Sofiane Takarabt, Alexander Schaub, Adrien Facon, Sylvain Guilley, Laurent Sauvage, et al.. Cache-Timing Attacks Still Threaten IoT Devices. International Conference on Codes, Cryptology, and Information Security, Apr 2019, Rabat, Morocco. pp.13-30, ⟨10.1007/978-3-030-16458-4_2⟩. ⟨hal-02319488⟩
  • Oualid Trabelsi, Laurent Sauvage, Jean-Luc Danger. Characterization at Logical Level of Magnetic Injection Probes. 2019 Joint International Symposium on Electromagnetic Compatibility and Asia-Pacific International Symposium on Electromagnetic Compatibility, Jun 2019, Sapporo, Japan. ⟨hal-02318716⟩
  • Sofiane Takarabt, Kais Chibani, Youssef Souissi, Laurent Sauvage, Sylvain Guilley, et al.. Pre-Silicon Embedded System Evaluation as new EDA for Security Verification. International Verification and Security Workshop (IVSW), Jun 2018, Platja d’Aro, Spain. ⟨hal-02287930⟩
  • Laurent Sauvage. Electromagnetic Fault Injection: from Attack to Countermeasure Design. CryptoIC, Sep 2017, Chengdu, China. ⟨hal-02287699⟩
  • Kazuhide Fukushima, Youssef Souissi, Seira Hidano, Robert Nguyen, Jean-Luc Danger, et al.. Delay PUF Assessment Method Based on Side-Channel and Modeling Analyzes. TrustCom-16, Aug 2016, Tianjin, China. ⟨hal-02287456⟩
  • Laurent Sauvage, Sofiane Takarabt, Youssef Souissi. Secure Silicon: Towards Virtual Prototyping. TRUDEVICE, Nov 2016, Barcelona, Spain. ⟨hal-02287467⟩
  • Laurent Sauvage. Injection électromagnétique de fautes sur FPGA : caractérisation & contre-mesure. CRYPTO'PUCES, May 2015, Porquerolles, France. ⟨hal-02287251⟩
  • Laurent Sauvage. Electromagnetic Fault injection: Impact on FPGA. Journée Sécurité Numérique du GDR SoC-SiP, Jun 2015, Paris, France. ⟨hal-02287253⟩
  • Lionel Rivière, Zakaria Najm, Pablo Rauzy, Jean-Luc Danger, Julien Bringer, et al.. High Precision Fault Injections on the Instruction Cache of ARMv7-M Architectures. HOST 2015: IEEE International Symposium on Hardware-Oriented Security and Trust, May 2015, Washington, United States. ⟨10.1109/HST.2015.7140238⟩. ⟨hal-01208378⟩
  • Yuto Nakano, Youssef Souissi, Robert Nguyen, Laurent Sauvage, Jean-Luc Danger, et al.. A Pre-processing Composition for Secret Key Recovery on Android Smartphone. 8th IFIP International Workshop on Information Security Theory and Practice (WISTP), Jun 2014, Heraklion, Crete, Greece. pp.76-91, ⟨10.1007/978-3-662-43826-8_6⟩. ⟨hal-01400921⟩
  • Laurent Sauvage. Electric Probes for Fault Injection Attack. APEMC, Aug 2013, Melbourne, Australia. ⟨hal-02286766⟩
  • Yu-Ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, et al.. Introduction to Recent Research on EM Information Leakage. Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC2013), May 2013, Melbourne, Australia. pp.320-323. ⟨hal-02286818⟩
  • Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Xuan Thuy Ngo, Laurent Sauvage. Hardware Trojan Horses in Cryptographic IP Cores. FDTC (Fault Detection and Tolerance in Cryptography), Aug 2013, Santa Barbara, United States. pp.15-29, ⟨10.1109/FDTC.2013.15⟩. ⟨hal-00855146v2⟩
  • Haruki Shimada, Yu-Ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, et al.. Efficient mapping of EM radiation associated with information leakage for cryptographic devices. EMC, Aug 2012, Pittsburgh, United States. pp.794-799, ⟨10.1109/ISEMC.2012.6351663⟩. ⟨hal-02288342⟩
  • Taoufik Chouta, Jean-Luc Danger, Laurent Sauvage, Tarik Graba. A Small and High-performance Coprocessor for Fingerprint Match-On-Card. DSD, Sep 2012, Cesme/Izmir, Turkey. ⟨10.1109/DSD.2012.14⟩. ⟨hal-02286419⟩
  • Sylvain Guilley, Olivier Meynard, Maxime Nassar, Guillaume Duc, Philippe Hoogvorst, et al.. Vade Mecum on Side-Channels Attacks and Countermeasures for the Designer and the Evaluator. Design & Technology of Integrated Systems, Apr 2011, Athens, Greece. pp.6, ⟨10.1109/DTIS.2011.5941419⟩. ⟨hal-00579020v2⟩
  • Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane. Fault Injection Resilience. Fault Diagnosis and Tolerance in Cryptography, Aug 2010, Santa Barbara, United States. pp.51-65, ⟨10.1109/FDTC.2010.15⟩. ⟨hal-00482194v9⟩
  • Houssem Maghrebi, Jean-Luc Danger, Florent Flament, Sylvain Guilley, Laurent Sauvage. Evaluation of Countermeasure Implementations Based on Boolean Masking to Thwart Side-Channel Attacks. SCS, Nov 2009, Jerba, Tunisia. 6 p., ⟨10.1109/ICSCS.2009.5412597⟩. ⟨hal-00425523v4⟩
  • Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, et al.. Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig, Dec 2009, Cancún, Mexico. pp.213 - 218, ⟨10.1109/ReConFig.2009.50⟩. ⟨hal-00411843v3⟩
  • Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar. Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints.. Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09., Apr 2009, NICE, France. pp.640-645. ⟨hal-00325417v3⟩
  • Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst. Area Optimization of Cryptographic Co-Processors Implemented in Dual-Rail with Precharge Positive Logic. International Conference on Field Programmable Logic and Applications, Sep 2008, Heidelberg, Germany. pp.161-166, ⟨10.1109/FPL.2008.4629925⟩. ⟨hal-00320425v2⟩
  • Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Tarik Graba, Jean-Luc Danger, et al.. Shall we trust WDDL?. Future of Trust in Computing, Jun 2008, Berlin, Germany. pp.208-215, ⟨10.1007/978-3-8348-9324-6_22⟩. ⟨hal-00409024⟩
  • Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet. Silicon-level Solutions to Counteract Passive and Active Attacks. FDTC, Aug 2008, Washington, DC, United States. pp.3-17, ⟨10.1109/FDTC.2008.18⟩. ⟨hal-00311431⟩
  • Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu. Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. Secure System Integration and Reliability Improvement, Jul 2008, Yokohama, Japan. pp.16-23, ⟨10.1109/SSIRI.2008.31⟩. ⟨hal-00259153v5⟩

Book sections1 document

  • Kais Chibani, Adrien Facon, Sylvain Guilley, Damien Marion, Yves Mathieu, et al.. Fault Analysis Assisted by Simulation. Automated Methods in Cryptographic Fault Analysis, Springer International Publishing, pp.263-277, 2019, ⟨10.1007/978-3-030-11333-9_12⟩. ⟨hal-02319491⟩

Preprints, Working Papers, ...3 documents

  • Jean-Luc Danger, Sylvain Guilley, Shivam Bhasin, Maxime Nassar, Laurent Sauvage. Overview of Dual Rail with Precharge Logic Styles to Thwart Implementation-Level Attacks on Hardware Cryptoprocessors. 2009. ⟨hal-00431261⟩
  • Laurent Sauvage, Sylvain Guilley, Yves Mathieu. ElectroMagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack of a Cryptographic Module. 2008. ⟨hal-00319164⟩
  • Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar. Successful Attack on an FPGA-based Automatically Placed and Routed WDDL+ Crypto Processor.. 2008. ⟨hal-00339858⟩

Reports1 document

  • Laurent Sauvage. Description des nouvelles attaques et de leurs caractéristiques en termes d'efficacité et de modèles de fautes. [Contrat] 2KCPV1206, Télécom ParisTech. 2014. ⟨hal-02286963⟩