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Laurent Fesquet

3
Documents

Présentation

Maître de conférences [Laboratoire TIMA](tima.imag.fr/ "Laboratoire TIMA") Equipe [CDSI](http://tima.imag.fr/tima/en/cdsi/cdsioverview.html "équipe CDSI") (Design of Integrated devices, Circuits and Systems)
Associate Professor [Laboratoire TIMA](tima.imag.fr/ "Laboratoire TIMA") Team: [CDSI](http://tima.imag.fr/tima/en/cdsi/cdsioverview.html "équipe CDSI") (Design of Integrated devices, Circuits and Systems)

Publications

774416
Image document

An Area and Power Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits

 Jérémy Belot , Abdelkarim Cherkaoui , Raphael Laurent , Laurent Fesquet
IEEE Design & Test, 2021, 38 (6), pp.69-77
Article dans une revue hal-03662193v1
Image document

An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study

 Jérémy Belot , Abdelkarim Cherkaoui , Raphael Laurent , Laurent Fesquet
28th IEEE International Conference on Electronics Circuits and Systems (ICECS 2021), Nov 2021, Dubai, United Arab Emirates. ⟨10.1109/ICECS53924.2021.9665535⟩
Communication dans un congrès hal-03662362v1

A practical framework for specification, verification and design of self-timed pipelines

 Jean Simatic , Abdelkarim Cherkaoui , Bertrand François , Rodrigo Possamai Bastos , Laurent Fesquet
23rd IEEE International Symposium on Asynchronous Circuits and Systems (Async 2017), May 2017, San Diego, CA, United States. pp.65-72, ⟨10.1109/ASYNC.2017.16⟩
Communication dans un congrès hal-01512247v1