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59 résultats
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triés par
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A Mixed Verification Strategy Tailored for Networks on ChipNoCS 2012 - 6th IEEE/ACM International Symposium on Networks-on-Chip, May 2012, Copenhagen, Denmark. pp.161-168, ⟨10.1109/NOCS.2012.26⟩
Communication dans un congrès
hal-00745086v1
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LogicielFrance, Patent n° : FR.001.220016.000.S.P.2009.000.31500. 2009
Brevet
hal-00578146v1
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Modélisation et Vérification Formelle des Circuits Digitaux: un état des recherches actuellesInternationale Conférence "Identification, Modelling and Simulation", Jun 1987, Paris, France
Communication dans un congrès
hal-01401525v1
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Assertion-Based Verification for the validation and safety analysis of hardware/software systems on chipTORRENTS Working day (RTRA Sciences et Technologies pour l'Aéronautique et l'Espace), Dec 2013, Toulouse, France
Communication dans un congrès
hal-00960603v1
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Automatic Refinement of Requirements for Verification throughout the SoC Design FlowInternational Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'13), Embedded Syst Week), Sep 2013, Montreal, Canada
Communication dans un congrès
hal-00919887v1
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Outils de démonstration automatique et preuve de circuits électroniquesForum Méthodes Formelles "Preuve de modèle, preuve de programme" (Aerospace Valley - Minalogic), Feb 2014, Toulouse, France
Communication dans un congrès
hal-01060383v1
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ISIS: Runtime Verification of TLM PlatformsAdvances in Design Methods from Modeling Languages for Embedded Systems and SoC's (Selected Contributions from FDL'09), Springer, pp.213-226, 2010, Lecture Notes in Electrical Engineering (vol. 63)
Chapitre d'ouvrage
hal-00518671v1
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Soft Error Effect and Register Criticality Evaluations: Past, Present and FutureIEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'09), Mar 2009, Stanford (CA), United States. pp.15-20
Communication dans un congrès
hal-00386113v1
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High-level symbolic simulation for automatic model extractionIEEE Symposium on Design and Diagnostics of Electronic Systems (DDECS'09), Apr 2009, Liberec, Czech Republic. pp.218-221, ⟨10.1109/DDECS.2009.5012132⟩
Communication dans un congrès
hal-00417314v1
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ACL2 for the Verification of Fault-Tolerance Properties: First ResultsInternational Workshop on The ACL2 Theorem Prover and Its Applications, May 2009, Boston (MA), United States. pp.90-99
Communication dans un congrès
hal-00418365v1
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A Generic Model for Formally Verifying NoC Communication Architectures: A Case StudyACM/IEEE International Symposium on Networks-on-Chips (NOCS'2007), Princeton (New Jersey), May 7-9, May 2007, Princeton, New Jersey, United States. pp.127-136, ⟨10.1109/NOCS.2007.1⟩
Communication dans un congrès
hal-00156745v1
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ACL2-based verification of the communications in the hermes network on chipInternational Workshop on Symbolic Methods and Applications to Circuit Design (SMACD'06), Oct 2006, Firenze, Italy. pp.1-6
Communication dans un congrès
hal-00142377v1
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Formalization of finite state machines with data path for the verification of high-level synthesisProceedings.-XI-Brazilian-Symposium-on-Integrated-Circuit-Design-Cat.-No.98EX216, 1998, Rio de Janeiro, Brazil. pp.99-102, ⟨10.1109/SBCCI.1998.715419⟩
Communication dans un congrès
hal-00014179v1
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Premiers résultats sur l'utilisation d'ACL2 pour l'évaluation de la conséquence des erreurs logiques2ème Colloque du GdR SoC-SiP, Jun 2008, Paris, France
Communication dans un congrès
hal-00323014v1
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A formal approach for the specification of communications in distributed systemsISCA 13th International Conference on Parallel and Distributed Computing Systems (PDCS'00), Aug 2000, Las Vegas, Nevada, United States
Communication dans un congrès
hal-01384162v1
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Design Understanding - At What Abstraction Level is the Pain Most Intense?Workshop on Design Automation for Understanding Hardware Designs (DUHDe Friday Workshop DATE 2015), Mar 2015, Grenoble, France
Communication dans un congrès
hal-01393830v1
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Towards a Toolchain for Assertion-Driven Test Sequence GenerationForum on specification & Design Languages (FDL’2015), Sep 2015, Barcelona, Spain
Communication dans un congrès
hal-01393417v1
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Auxiliary Variables in Temporal Specifications: Semantic and Practical Analysis for System-Level RequirementsACM Transactions on Design Automation of Electronic Systems, 2016, 21 (2), pp.Article n°20. ⟨10.1145/2811260⟩
Article dans une revue
hal-01332715v1
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A Customizable Monitoring Infrastructure for Hardware/Software Embedded Systems26th IFIP International Conference on Testing Software and Systems (ICTSS), Sep 2014, Madrid, Spain. pp.173-179, ⟨10.1007/978-3-662-44857-1_12⟩
Communication dans un congrès
hal-01405284v1
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A Tool for the Automatic TLM-to-RTL Conversion of Embedded Systems Requirements for a Seamless Verification FlowInternational Conference on Very Large Scale Integration (VLSI-SoC'14), Oct 2014, Playa del Carmen, Mexico, Mexico. pp.1-6
Communication dans un congrès
hal-01131944v1
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Runtime verification of functional requirements for SoC models: integration of PSL in SystemC TLMEcole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes, Jan 2013, Leysin, Switzerland
Communication dans un congrès
hal-01060026v1
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Formal proofs from HDL descriptionsFundamentals and Standards in Hardware Description Languages, 249, Springer, pp.155-194, 1993, NATO ASI Series (Series E: Applied Sciences), 978-94-011-1914-6. ⟨10.1007/978-94-011-1914-6_5⟩
Chapitre d'ouvrage
istex
hal-01469542v1
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A compositional model for the functional verification of high-level synthesis resultsIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000, Oct. ; 8(5), pp.526-30. ⟨10.1109/92.894157⟩
Article dans une revue
hal-00014163v1
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Dynamic Verification of SystemC Transactional ModelsJustyna Zander, Ina Schieferdecker, Pieter J. Mosterman. Model-Based Testing for Embedded Systems, CRC press, chapter 22, 2011
Chapitre d'ouvrage
hal-00653490v1
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Functional modelling and testing of digital circuitsRevue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, 1989, 8(6), pp.523-44
Article dans une revue
hal-00014306v1
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Runtime Verification of Typical Requirements for a Space Critical SoC Platform16th International Workshop on Formal Methods for Industrial Critical Systems (FMICS'11), Aug 2011, Trento, Italy. pp.21-36, ⟨10.1007/978-3-642-24431-5_4⟩
Communication dans un congrès
istex
hal-00644103v1
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On the Effectiveness of Assertion-Based Verification in an Industrial Context18th International Workshop on Formal Methods for Industrial Critical Systems (FMICS'2013), Sep 2013, Madrid, Spain. pp.78-93, ⟨10.1007/978-3-642-41010-9_6⟩
Communication dans un congrès
istex
hal-00920024v1
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Formal verification of CASCADE descriptionsInternational Working Conference on the fusion of hardware design and verification, Jul 1988, Glasgow, Scotland, United Kingdom
Communication dans un congrès
hal-01400772v1
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Runtime Verification of Embedded Systems Requirements throughout the Design FlowEcole d'hiver Francophone sur les Technologies de Conception des Systèmes embarqués Hétérogènes (FETCH'2015), Jan 2015, Louvain-La-Neuve, Belgium
Communication dans un congrès
hal-01132482v1
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A Formal Framework for Testing with Assertion Checkers in Mixed-Signal SimulationIEEE International Conference on Electronics, Circuits, and Systems (ICECS'2012), Dec 2012, Seville, Spain. pp.284 - 287, ⟨10.1109/ICECS.2012.6463745⟩
Communication dans un congrès
hal-00815923v1
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