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80 résultats
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Models of Architecture[Research Report] PREESM/2015-12TR01, 2015, IETR/INSA Rennes; Scuola Superiore Sant’Anna, Pisa; Institut Pascal, Clermont Ferrand; University of Maryland, College Park; Tampere University of Technology, Tampere. 2015
Rapport
hal-01244470v1
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CASSIS: Characterization with Adaptive Sample-Size Inferential Statistics Applied to Inexact CircuitsEUSIPCO: EUropean SIgnal Processing Conference, Sep 2018, Rome, Italy. ⟨10.23919/eusipco.2018.8553451⟩
Communication dans un congrès
hal-01879628v2
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SCAPE: HW-Aware Clustering of Dataflow Actors for Tunable Scheduling ComplexityDASIP 2023 - Workshop on Design and Architectures for Signal and Image Processing, HiPEAC, Jan 2023, Toulouse, France. pp.3-14, ⟨10.1007/978-3-031-29970-4_1⟩
Communication dans un congrès
hal-04089941v1
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Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow GraphsEmbedded Computer Systems: Architectures, Modeling, and Simulation, Jul 2019, Pythagorion, Samos Island, Greece. pp.269-280, ⟨10.1007/978-3-030-27562-4_19⟩
Communication dans un congrès
hal-02267487v2
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Dataflow Modeling for Reconfigurable Signal Processing SystemsHandbook of Signal Processing Systems, 3rd Edition, pp.787-824, 2019, ⟨10.1007/978-3-319-91734-4_22⟩
Chapitre d'ouvrage
hal-01899410v1
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Memory Study and Dataflow Representations for Rapid Prototyping of Signal Processing Applications on MPSoCsSignal and Image processing. INSA de Rennes, 2014. English. ⟨NNT : 2014ISAR0004⟩
Thèse
tel-01127297v1
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Automatic Generation of S-LAM Descriptions from UML/MARTE for the DSE of Massively Parallel Embedded SystemsRoger Lee. Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing 2015, 612, Springer, pp.195-211, 2016, Studies in Computational Intelligence, 978-3-319-23509-7. ⟨10.1007/978-3-319-23509-7_14⟩
Chapitre d'ouvrage
hal-01252511v1
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CERBERO Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable systems in unceRtain hybRid envirOnments16th ACM International Conference on Computing Frontiers, CF 2019, Apr 2019, Alghero, Italy. pp.320-325, ⟨10.1145/3310273.3323436⟩
Communication dans un congrès
hal-02161022v1
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Delays and States in Dataflow Models of ComputationSAMOS XVIII, Jul 2018, Pythagorion, Greece. ⟨10.1145/3229631.3229645⟩
Communication dans un congrès
hal-01850252v1
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Energy-Efficient Actor Execution for SDF Application on Heterogeneous Architectures26th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2018, Mar 2018, Cambridge, United Kingdom. pp.486-493, ⟨10.1109/PDP2018.2018.00083⟩
Communication dans un congrès
hal-01834878v1
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Real-Time Low Power Software HEVC Decoder on Embedded GPP: A Side-by-Side ComparisonDesign and Architectures for Signal and Image Processing (DASIP), Sep 2015, Cracow, Poland
Communication dans un congrès
hal-01205912v1
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Adaptive Simulation-based Framework for Error Characterization of Inexact CircuitsMicroelectronics Reliability, 2019, 96, pp.60-70. ⟨10.1016/j.microrel.2019.02.007⟩
Article dans une revue
hal-02094908v1
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Video Coding for Machines: Large-Scale Evaluation of Deep Neural Networks Robustness to Compression Artifacts for Semantic SegmentationInternational Workshop on Multimedia Signal Processing (MMSP), Sep 2022, Shanghai, China
Communication dans un congrès
hal-03831514v1
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Throughput Evaluation of DSP Applications based on Hierarchical Dataflow ModelsInternational Symposium on Circuits and Systems (ISCAS), May 2017, Baltimore, United States. ⟨10.1109/ISCAS.2017.8050774⟩
Communication dans un congrès
hal-01514641v1
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Gegelati: Lightweight Artificial Intelligence through Generic and Evolvable Tangled Program GraphsWorkshop on Design and Architectures for Signal and Image Processing (DASIP), Jan 2021, Budapest, Hungary. ⟨10.1145/3441110.3441575⟩
Communication dans un congrès
hal-03057652v2
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PAPIFY: Automatic Instrumentation and Monitoring of Dynamic Dataflow Applications Based on PAPIIEEE Access, 2019, 7, pp.111801-111812. ⟨10.1109/ACCESS.2019.2934223⟩
Article dans une revue
hal-02302609v1
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Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore ArchitecturesPARMA-DITAM, Jan 2018, Manchester, United Kingdom. ⟨10.1145/3183767.3183780⟩
Communication dans un congrès
hal-01704702v1
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PiSDF: Parameterized & Interfaced Synchronous Dataflow for MPSoCs Runtime Reconfiguration1st Workshop on MEthods and TOols for Dataflow PrOgramming (METODO), ECSI, Oct 2014, Madrid, Spain
Communication dans un congrès
hal-01075114v1
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Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal ProcessingJournal of Signal Processing Systems, 2016, 83 (3), pp.309-328. ⟨10.1007/s11265-014-0956-2⟩
Article dans une revue
hal-01075092v1
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Automatic instrumentation of dataflow applications using PAPI15th ACM International Conference on Computing Frontiers, CF 2018, May 2018, Ischia, Italy. pp.232-235, ⟨10.1145/3203217.3209886⟩
Communication dans un congrès
hal-01881032v1
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Analysis of the Impact of Approximate Computing on the Application QualityApproximate Computing Techniques: From Component- to Application-Level, Springer, pp.145-176, 2022, ⟨10.1007/978-3-030-94705-7_6⟩
Chapitre d'ouvrage
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An Initial Framework for Prototyping the Radio-Interferometric Imaging PipelinesDASIP 2024 - Workshop on Design and Architectures for Signal and Image Processing, HiPEAC, Jan 2024, Munich, Germany
Communication dans un congrès
hal-04361151v3
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SECURE-GEGELATI Always-On Intrusion Detection through GEGELATI Lightweight Tangled Program GraphsJournal of Signal Processing Systems, 2022, Design and Architectures for Signal and Image Processing 2021, 94 (7), pp.753-770. ⟨10.1007/s11265-021-01728-1⟩
Article dans une revue
hal-03554393v1
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DAMHSE Programming heterogeneous MPSoCs with hardware acceleration using dataflow-based design space exploration and automated rapid prototypingMicroprocessors and Microsystems: Embedded Hardware Design , 2019, 71, pp.102882. ⟨10.1016/j.micpro.2019.102882⟩
Article dans une revue
hal-02309549v1
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Models of Architecture: Application to ESL Model-Based Energy Consumption Estimation[Research Report] IETR/INSA Rennes; Scuola Superiore Sant’Anna, Pisa; Institut Pascal; University of Maryland, College Park; Tampere University of Technology, Tampere. 2017
Rapport
hal-01464856v1
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Hierarchical Dataflow Model for Efficient Programming of Clustered Manycore Processors28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2017), Jul 2017, Seattle, WA, United States
Communication dans un congrès
hal-01564019v1
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Memory Bounds for the Distributed Execution of a Hierarchical Synchronous Data-Flow Graph12th International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS XII), Jul 2012, Agios Konstantinos, Greece. pp.160
Communication dans un congrès
hal-00721335v1
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Numerical Representation of Directed Acyclic Graphs for Efficient Dataflow Embedded Resource AllocationACM Transactions on Embedded Computing Systems (TECS), 2019, 18 (5), pp.101. ⟨10.1145/3358225⟩
Article dans une revue
hal-02355636v1
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Demonstrating the SPIDER Runtime for Reconfigurable Dataflow Graphs Execution onto a DMA-based Manycore ProcessorIEEE International Workshop on Signal Processing Systems, Oct 2017, Lorient, France. 2017
Poster de conférence
hal-01637300v1
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Ultra-Fast Machine Learning Inference through C Code Generation for Tangled Program Graphs2022 IEEE Workshop on Signal Processing Systems (SiPS), Nov 2022, Rennes, France. pp.1-6, ⟨10.1109/SiPS55645.2022.9919237⟩
Communication dans un congrès
hal-03845227v1
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