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131 résultats
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Implementation of a Fast Fourier Transform Algorithm onto a Manycore ProcessorConference on Design and Architectures for Signal and Image Processing (DASIP), Sep 2015, Cracow, Poland. ⟨10.1109/dasip.2015.7367270⟩
Communication dans un congrès
hal-01238833v1
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Intégration de services vidéo Mpeg sur architectures parallèlesCalcul parallèle, distribué et partagé [cs.DC]. INSA RENNES, 2002. Français. ⟨NNT : 2002ISAR0008⟩
Thèse
tel-04292101v1
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Manycore Embedded processors for portable, optimized and power efficient processing of methods for vision algorithmsEuropean Machine Vision Forum 2017 (EMVF), Sep 2017, Viennes, Austria
Communication dans un congrès
hal-02505927v1
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An Open Framework for Rapid Prototyping of Signal Processing ApplicationsEURASIP Journal on Embedded Systems, 2009, vol 2009, pp14
Article dans une revue
hal-00429312v1
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Estimateur de mouvement temps réel multi-DSP pour l'encodage vidéo MPEG-4 AVC/H.264 haute définitionOct 2006, pp.NC
Communication dans un congrès
hal-00125363v1
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The Study of the impact of architecture design on cognitive radioProceedings of the 8th IEEE International Multi-Conference on Systems, Signals & Devices (SSD), Mar 2011, Sousse, Tunisia. pp.CD
Communication dans un congrès
hal-00661410v1
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On Memory Reuse Between Inputs and Outputs of Dataflow ActorsACM Transactions on Embedded Computing Systems (TECS), 2016, 15 (2), pp.30. ⟨10.1145/2871744⟩
Article dans une revue
hal-01284333v1
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A Fast Heuristic to Pipeline SDF GraphsEmbedded Computer Systems: Architectures, Modeling, and Simulation, Jul 2020, Pythagorion, Samos Island, Greece. pp.139-151, ⟨10.1007/978-3-030-60939-9_10⟩
Communication dans un congrès
hal-02993338v1
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Buffer Merging Technique for Minimizing Memory Footprints of Synchronous Dataflow SpecificationsInternational Conference on Acoustics, Speech and Signal Processing (ICASSP), Apr 2015, Brisbane, Australia. pp.1111-1115, ⟨10.1109/icassp.2015.7178142⟩
Communication dans un congrès
hal-01146340v1
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Generation of Efficient High-Level Hardware Code from Dataflow ProgramsDesign, Automation and test in Europe (DATE), Mar 2012, Dresden, Germany. pp.NC
Communication dans un congrès
hal-00763804v1
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Relaxed Subgraph Execution Model for the Throughput Evaluation of IBSDF GraphsInternational Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Jul 2017, SAMOS, Greece. ⟨10.1109/SAMOS.2017.8344630⟩
Communication dans un congrès
hal-01569593v1
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Demonstrating a Dataflow-based RTOS for Heterogeneous MPSoC by means of a Stereo Matching ApplicationDASIP 2014, Oct 2014, Madrid, Spain
Communication dans un congrès
hal-01101788v1
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A comparison of cost construction methods onto a C6678 platform for stereo matching2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), Oct 2016, Rennes, France. ⟨10.1109/DASIP.2016.7853821⟩
Communication dans un congrès
hal-01420790v1
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Software synthesis of CAL actors for the MPEG reconfigurable Video Coding frameworkImage Processing, 2008. ICIP 2008. 15th IEEE International Conference on, Oct 2008, San Diego, United States. pp.1408 - 1411, ⟨10.1109/ICIP.2008.4712028⟩
Communication dans un congrès
hal-00336481v1
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A codesign synthesis from an MPEG-4 decoder dataflow descriptionCircuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, May 2010, Paris, France. pp.1995 -1998, ⟨10.1109/ISCAS.2010.5537107⟩
Communication dans un congrès
hal-00560031v1
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Building a RTOS for MPSoC Dataflow Programming2011 International Symposium on System on Chip (SoC), Oct 2011, Finland. pp.143
Communication dans un congrès
hal-00658848v1
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SynDEx executive kernel development for DSPs TI C6x applied to real-time and embedded multiprocessors architectures2002, Volume II pp 213-216
Communication dans un congrès
hal-00124987v1
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PREESM: A Dataflow-Based Rapid Prototyping Framework for Simplifying Multicore DSP ProgrammingEDERC, Sep 2014, Italy. pp.36
Communication dans un congrès
hal-01059313v1
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Automated Clustering and Pipelining of Dataflow Actors for Controlled Scheduling ComplexityEUSIPCO, EURASIP, Sep 2023, Helsiinki, Finland
Communication dans un congrès
hal-04253298v1
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PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration13th International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS XIII), Jul 2013, Samos, Greece. pp.41 - 48, ⟨10.1109/SAMOS.2013.6621104⟩
Communication dans un congrès
hal-00877492v2
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AN EXPERIMENTAL TOOLCHAIN BASED ON HIGH-LEVEL DATAFLOW MODELS OF COMPUTATION FOR HETEROGENEOUS MPSOCDASIP, Oct 2012, Karlsruhe, Germany
Communication dans un congrès
hal-00749175v1
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FPGA Dynamic Reconfiguration using the RVC Technology: Inverse Quantization Case StudyConference on Design and Architectures for Signal and Image Processing (DASIP), Nov 2011, Tampere, Finland. pp.CD
Communication dans un congrès
hal-00661337v1
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Throughput Evaluation of DSP Applications based on Hierarchical Dataflow ModelsInternational Symposium on Circuits and Systems (ISCAS), May 2017, Baltimore, United States. ⟨10.1109/ISCAS.2017.8050774⟩
Communication dans un congrès
hal-01514641v1
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Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore ArchitecturesPARMA-DITAM, Jan 2018, Manchester, United Kingdom. ⟨10.1145/3183767.3183780⟩
Communication dans un congrès
hal-01704702v1
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Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal ProcessingJournal of Signal Processing Systems, 2016, 83 (3), pp.309-328. ⟨10.1007/s11265-014-0956-2⟩
Article dans une revue
hal-01075092v1
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Optimization of the motion estimation for parallel embedded systems in the context of new video standardsSPIE Optics + Photonics, Aug 2012, San Diego, United States. pp.849917, ⟨10.1117/12.939469⟩
Communication dans un congrès
hal-00760947v1
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IMPLEMENTATION OF MOTION ESTIMATION BASED ON HETEROGENEOUS PARALLEL COMPUTING SYSTEM WITH OPENC14th IEEE International Conference on High Performance Computing and Communications (HPCC), Jun 2012, Liverpool, United Kingdom. pp.NC
Communication dans un congrès
hal-00763860v1
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A HIERARCHICAL IMPLEMENTATION OF HADAMARD TRANSFORM USING RVC-CAL DATAFLOW PROGRAMMING AND DYNAMIC PARTIAL RECONFIGURATIONConference on Design and Architectures for Signal and Image Processing (DASIP), Oct 2012, Karlsruhe, Germany. pp.NC
Communication dans un congrès
hal-00763876v1
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An Initial Framework for Prototyping the Radio-Interferometric Imaging PipelinesDASIP 2024 - Workshop on Design and Architectures for Signal and Image Processing, HiPEAC, Jan 2024, Munich, Germany
Communication dans un congrès
hal-04361151v3
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Reconfigurable Video Coding on multicore : an overview of its main objectivesIEEE Signal Processing Magazine, 2009, Volume 26 (Issue 6), pp 113 - 123. ⟨10.1109/MSP.2009.934107⟩
Article dans une revue
hal-00429360v1
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