CV

Philippe Chiquet, Maxime Chambonneau, V. Della Marca, Jérémy Postel-Pellerin, Pierre Canet, et al.. Phenomenological modelling of non-volatile memory threshold voltage shift induced by nonlinear ionization with a femtosecond laser. Scientific Reports, Nature Publishing Group, 2019, 9 (7392), ⟨10.1038/s41598-019-43344-x⟩. ⟨hal-02137915⟩

V. Della Marca, J. Postel-Pellerin, T. Kempf, A. Regnier, P. Chiquet, et al.. Quantitative correlation between Flash and equivalent transistor for endurance electrical parameters extraction. Microelectronics Reliability, Elsevier, 2018, 88-90, pp.159 - 163. ⟨10.1016/j.microrel.2018.06.116⟩. ⟨hal-01900789⟩

Maxime Chambonneau, Sarra Souiki-Figuigui, Philippe Chiquet, Vincenzo Marca, Jérémy Postel-Pellerin, et al.. Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations. Applied Physics Letters, American Institute of Physics, 2017, 110, pp.161112 - 161112. ⟨hal-01655116⟩

P. Chiquet, J. Postel-Pellerin, C. Tuninetti, S. Souiki-Figuigui, P. Masson. Enhancement of flash memory endurance using short pulsed program/erase signals. ACTA IMEKO, International Measurement Confederation (IMEKO), 2016, 5 (4), pp.29-36. ⟨10.21014/acta_imeko.v5i4.422⟩. ⟨hal-01451431⟩

P. Canet, J. Postel-Pellerin, Hassen Aziza. Impact of resistive paths on NVM array reliability: Application to Flash & ReRAM memories. Microelectronics Reliability, Elsevier, 2016, 64 (SI), pp.36-41. ⟨10.1016/j.microrel.2016.07.096⟩. ⟨hal-01434941⟩

V. Della Marca, J. Postel-Pellerin, G. Just, P. Canet, J.-L. Ogier. Impact of endurance degradation on the programming efficiency and the energy consumption of NOR flash memories. Microelectronics Reliability, Elsevier, 2014, 54 (9-10), pp.2262 - 2265. ⟨10.1016/j.microrel.2014.07.063⟩. ⟨hal-01760459⟩

Philippe Chiquet, Pascal Masson, Jérémy Postel-Pellerin, Romain Laffont, Gilles Micolau, et al.. Experimental setup for non-destructive measurement of tunneling currents in semiconductor devices. Measurement, Elsevier, 2014, ⟨10.1016/j.measurement.2014.02.015⟩. ⟨hal-01315418⟩

V. Della Marca, J. Amouroux, G. Molas, J. Postel-Pellerin, F. Lalande, et al.. Improved Performance of Silicon Nanocrystal Memories for Application Working Over a Wide Range of Temperature. ECS Transactions, Electrochemical Society, Inc., 2013, 53 (4), pp.129 - 139. ⟨10.1149/05304.0129ecst⟩. ⟨hal-01760473⟩

V. Della Marca, G. Just, A. Regnier, L. Ogier, R. Simola, et al.. Push the flash floating gate memories toward the future low energy application. Solid-State Electronics, Elsevier, 2013, 79, pp.210 - 217. ⟨10.1016/j.sse.2012.09.001⟩. ⟨hal-01760461⟩

Guillaume Just, V. Della Marca, Arnaud Regnier, Jean-Luc Ogier, Jérémy Postel-Pellerin, et al.. Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability. Journal of Low Power Electronics, American Scientific Publishers, 2012, 8 (5), pp.717 - 724. ⟨10.1166/jolpe.2012.1230⟩. ⟨hal-01760474⟩

H. Aziza, H. Bazzi, J. Postel-Pellerin, P. Canet, M. Moreau, et al.. An Augmented OxRAM Synapse for Spiking Neural Network (SNN) Circuits. 2019 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), Apr 2019, Mykonos, France. ⟨10.1109/DTIS.2019.8735057⟩. ⟨hal-02306907⟩

M. Kharbouche-Harrari, Rana Alhalabi, J. Postel-Pellerin, Romain Wacquez, Driss Aboulkassimi, et al.. MRAM: from STT to SOT, for security and memory. XXXIII CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS), Nov 2018, Lyon, France. ⟨hal-01982788⟩

M. Kharbouche-Harrari, J. Postel-Pellerin, G. Di Pendina, R. Wacquez, D. Aboulkassimi, et al.. Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues. 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS), Jul 2018, Platja d'Aro, Spain. ⟨hal-01976697⟩

Hassen Aziza, P. Canet, J. Postel-Pellerin, Mathieu Moreau, Jean-Michel Portal, et al.. ReRAM ON/OFF resistance ratio degradation due to line resistance combined with device variability in 28nm FDSOI technology. 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2017, Athens, Greece. ⟨10.1109/ULIS.2017.7962594⟩. ⟨hal-01745666⟩

G. Micolau, J. Postel-Pellerin, P. Chiquet, M. Joelson, C. Abbas, et al.. Toward an innovative stochastic modeling of electric charges losses trough dielectrics . Inter-Disciplinary Underground Science and Technology (i-DUST) Conference, Jun 2016, Avignon, France. ⟨10.1051/e3sconf/20161204004⟩. ⟨hal-01451874⟩

J. Postel-Pellerin, P. Chiquet, V. Della Marca. Simulation of the programming efficiency and the energy consumption of Flash memories during endurance degradation. International Semiconductor Conference (CAS), 2016, Oct 2016, Sinaia, Romania. ⟨10.1109/SMICND.2016.7783052⟩. ⟨hal-01436469⟩

P. Chiquet, J. Postel-Pellerin, C. Tuninetti, S. Souiki-Figuigui, P. Masson. Effect Of Short Pulsed Program/Erase Cycling On Flash Memory Devices. Workshop on New Perspectives in Measurements, Tools and Techniques for system’s reliability, maintainability and safety, Jun 2016, Milan, Italy. ⟨hal-01437034⟩

V. Della Marca, M. Chambonneau, S. Souiki-Figuigui, J. Postel-Pellerin, P. Canet, et al.. NVM cell degradation induced by femtosecond laser backside irradiation for reliability tests. 2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2016, Unknown, Unknown Region. ⟨hal-01418479⟩

T. Sarno, R. Wacquez, Edith Kussener, P. Maurine, K. Jradi, et al.. Electromagnetic Analysis Perturbation using Chaos Generator . Truedevice 2016, Nov 2016, Barcelona, Spain. ⟨hal-01455446⟩

P. Canet, J. Postel-Pellerin, Hassen Aziza. Impact of Resistive Paths on NVM Array Reliability: Application to Flash & ReRAM Memories. 27th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2016), Sep 2016, Halle, Germany. ⟨hal-01463140⟩

J. Postel-Pellerin, P. Chiquet, Gilles Micolau, D. Boyer. Indirect measurement of low tunneling currents through dielectrics using floating gate structures. IEEE International Conference on Dielectrics (ICD) , Jul 2016, Montpellier, France. pp.1065-1068. ⟨hal-01594071⟩

Jonathan Bartoli, V. Della Marca, Jérémy Postel-Pellerin, Julien Delalleau, Arnaud Regnier, et al.. Optimization of the ATW Non-Volatile Memory for Connected Smart Objects. 2015 IEEE International Memory Workshop (IMW), May 2015, Monterey, France. ⟨10.1109/IMW.2015.7150299⟩. ⟨hal-01760536⟩

J. Postel-Pellerin, P. Chiquet, V. Della Marca, T. Wakrim, G. Just, et al.. Improving Flash memory endurance and consumption with ultra-short channel-hot-electron programming pulses. 2014 International Semiconductor Conference (CAS), Oct 2014, Sinaia, France. ⟨10.1109/SMICND.2014.6966433⟩. ⟨hal-01760566⟩

J. Bartoli, V. Della Marca, J. Delalleau, A. Regnier, S. Niel, et al.. A new non-volatile memory cell based on the flash architecture for embedded low energy applications: ATW (Asymmetrical Tunnel Window). 2014 International Semiconductor Conference (CAS), Oct 2014, Sinaia, France. ⟨10.1109/SMICND.2014.6966409⟩. ⟨hal-01760564⟩

V. Della Marca, T. Wakrim, J. Postel-Pellerin, P. Canet. Advanced experimental setup for reliability and current consumption measurements of Flash non-volatile memories. IMEKO TC4, Sep 2014, Benevento, Italy. ⟨hal-01760548⟩

V. Della Marca, L. Masoero, J. Postel-Pellerin, F. Lalande, J. Amouroux, et al.. Dynamic behavior of silicon nanocrystal memories during the hot carrier injection. 2013 IEEE International Conference on Solid Dielectrics (ICSD), Jun 2013, Bologna, France. ⟨10.1109/ICSD.2013.6619820⟩. ⟨hal-01760571⟩

P. Chiquet, P. Masson, Gilles Micolau, R. Laffont, F. Lalande, et al.. Determination of physical properties of semiconductor-oxide-semiconductor structures using a new fast gate current measurement protocol.. 11th IEEE International Conference on Solid Dielectrics , Jul 2013, Bologne, Italy. ⟨hal-01315415⟩

V. Della Marca, J. Amouroux, G. Molas, J. Postel-Pellerin, F. Lalande, et al.. How to improve the silicon nanocrystal memory cell performances for low power applications. 2012 International Semiconductor Conference (CAS 2012), Oct 2012, Sinaia, France. ⟨10.1109/SMICND.2012.6400686⟩. ⟨hal-01760587⟩

V. Della Marca, L. Masoero, G. Molas, J. Amouroux, E. Petit-Faivre, et al.. Optimization of programming consumption of silicon nanocrystal memories for low power applications. 2012 International Semiconductor Conference Dresden-Grenoble (ISCDG) - formerly known as the Semiconductor Conference Dresden (SCD), Sep 2012, Grenoble, France. ⟨10.1109/ISCDG.2012.6359988⟩. ⟨hal-01760573⟩

V. Della Marca, A. Regnier, J. Ogier, R. Simola, S. Niel, et al.. Experimental study to push the Flash floating gate memories toward low energy applications. 2011 International Semiconductor Device Research Symposium (ISDRS), Dec 2011, College Park, France. ⟨10.1109/ISDRS.2011.6135271⟩. ⟨hal-01760595⟩

V. Della Marca, Julien Amouroux, Julien Delalleau, Laurent Lopez, Jean-Luc Ogier, et al.. Energy consumption optimization in nonvolatile silicon nanocrystal memories. 2011 International Semiconductor Conference (CAS 2011), Oct 2011, Sinaia, France. ⟨10.1109/SMICND.2011.6095810⟩. ⟨hal-01760593⟩

V. Della Marca, J. Postel-Pellerin, G. Just, P. Canet, J.-L. Ogier. Programming optimization for low energy NOR Flash memories. Non-Volatile Memory Workshop, Mar 2015, San Diego, United States. ⟨hal-01760653⟩

J. Bartoli, V. Della Marca, Julien Delalleau, Arnaud Regnier, S. Niel, et al.. A new flash architecture for embedded low energy applications: ATW (Asymmetrical Tunnel Window). Non-Volatile Memory Workshop, Mar 2014, San Diego, United States. ⟨hal-01760651⟩

Jérémy Postel-Pellerin. Fiabilité des Mémoires Non-Volatiles de type Flash en architectures NOR et NAND. Micro et nanotechnologies/Microélectronique. Université de Provence - Aix-Marseille I, 2008. Français. ⟨tel-00370377⟩