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152 résultats
A new single-error correction scheme based on self-diagnosis residue number arithmeticDASIP 2010 : Design and Architectures for Signal and Image Processing, Oct 2010, Edinburgh, United Kingdom
Communication dans un congrès
hal-01170765v1
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High data rate and flexible hardware QC-LDPC decoder for satellite optical communications2018 IEEE 10th International Symposium on Turbo Codes & Iterative Information Processing (ISTC), Dec 2018, Hong Kong, China. pp.1-5
Communication dans un congrès
hal-02003000v1
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Méthodologie d'optimisation des processeurs embarques : Une approche favorisant la réduction de la surface et de la consommation des processeurs embarquésRevue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, 2013, 32 (6), pp.725-754. ⟨10.3166/TSI.32.725-754⟩
Article dans une revue
hal-00987580v1
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From multicore LDPC decoder implementations to FPGA decoder architectures: a case study2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec 2018, Bordeaux, France. pp.89-92
Communication dans un congrès
hal-02002993v1
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A Flexible NISC-Based LDPC DecoderIEEE Transactions on Signal Processing, 2014, 62 (10), pp.2469-2479. ⟨10.1109/TSP.2014.2311964⟩
Article dans une revue
hal-00984961v1
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Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit2005, pp.263-266
Communication dans un congrès
hal-00083398v1
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Prototypage d'un récepteur itératif pour des systèmes MIMOGDR SoC-SiP : Groupe de recherche system on chip -system in package, Jun 2009, Paris, France
Communication dans un congrès
hal-00446925v1
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Stochastic multiple-stream decoding of Cortex codesIEEE Transactions on Signal Processing, 2011, 59 (7), pp.3486 - 3491
Article dans une revue
hal-00617865v1
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A shuffled iterative bit-interleaved coded modulation receiver for the DVB-T2 standard: Design, implementation and FPGA prototypingSignal Processing Systems (SiPS), 2011 IEEE Workshop on, Oct 2011, Beirut, Lebanon. pp.55 -60, ⟨10.1109/SiPS.2011.6088949⟩
Communication dans un congrès
hal-00667672v1
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Design and implementation of a soft-decision decoder for Cortex codesICECS 2010 IEEE international conference on electronics, circuits, and systems, Dec 2010, Athens, Greece. pp.663 - 666
Communication dans un congrès
hal-00617881v1
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On the higher efficiency of parallel Reed-Solomon turbo-decodingElectronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on, Aug 2008, St. Julian's, Malta. pp.1308 -1311, ⟨10.1109/ICECS.2008.4675100⟩
Communication dans un congrès
hal-00538607v1
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Towards Gb/s turbo decoding of product code onto an FPGA deviceCircuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, May 2007, New Orleans, United States. pp.909 -912, ⟨10.1109/ISCAS.2007.378073⟩
Communication dans un congrès
hal-00538609v1
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OFDM-IDMA versus IDMA with ISI cancellation for quasi-static Rayleigh fading multipath channels4th International Symposium on turbo codes and related topics, April 3-7, Munich, Germany, Apr 2006, Munich, Germany
Communication dans un congrès
hal-01874742v1
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Efficient architecture for Reed Solomon block turbo codeISCAS 2006 : IEEE International Symposium on Circuits And Systems, May 2006, Kos, Greece. pp.3682 - 3685, ⟨10.1109/ISCAS.2006.1693426⟩
Communication dans un congrès
hal-01876239v1
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High speed low complexity radix-16 Max-Log-MAP SISO decoderICECS 2012 : 19th IEEE International Conference on Electronics, Circuits and Systems, Dec 2012, Séville, France. pp.400-403, ⟨10.1109/ICECS.2012.6463718⟩
Communication dans un congrès
hal-00955749v1
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Fast and Flexible Software Polar List DecodersJournal of Signal Processing Systems, 2019, ⟨10.1007/s11265-018-1430-3⟩
Article dans une revue
hal-01987848v1
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High speed LDPC decoding for optical space link2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov 2020, Glasgow, United Kingdom. pp.1-4, ⟨10.1109/ICECS49266.2020.9294911⟩
Communication dans un congrès
hal-03327792v1
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Fair comparison of hardware and software LDPC decoder implementations for SDR space links2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nov 2020, Glasgow, United Kingdom. pp.1-4, ⟨10.1109/ICECS49266.2020.9294906⟩
Communication dans un congrès
hal-03327797v1
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Techniques and Prospects for Fault-tolerance in Post-CMOS ULSIULSIWS 2012: 21st International Workshop on Post-Binary ULSI Systems, May 2012, France. pp.1-7
Communication dans un congrès
hal-00955755v1
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Fine Grain Parallel Decoding of Turbo Product Codes: Algorithm and Architecture5th international symposium on turbo codes and related topics, Sep 2008, Lausanne, Switzerland. pp.90-95
Communication dans un congrès
hal-00487334v1
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Near maximum likelihood soft-decision decoding of a particular class of rate-1/2 systematic linear block codesElectronics Letters, 2011, 47 (4), pp.259 -260. ⟨10.1049/el.2010.7857⟩
Article dans une revue
hal-00573239v1
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Muller C-element based Decoder (MCD): A decoder against transient faultsCircuits and Systems (ISCAS), 2013 IEEE International Symposium on, May 2013, Beijing, China. pp.1680-1683, ⟨10.1109/ISCAS.2013.6572187⟩
Communication dans un congrès
hal-00955725v1
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The Case Study of Block turbo Decoders on a Framework for Portable Synthesis on FPGA39th Hawaii International conference on System Sciences, 2006, United States. pp.250b
Communication dans un congrès
hal-00083395v1
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Abstract Synthesis of Turbo Decoder Elements onto Reconfigurable Circuit2005, pp.263-264
Communication dans un congrès
hal-00079265v1
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An LP-based algorithm for decoding terminated LDPC convolutional codes2017 International Conference on Internet of Things, Embedded Systems and Communications (IINTEC), Oct 2017, Gafsa, France. pp.95-100
Communication dans un congrès
hal-02003010v1
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GPU-Like On-Chip System for Decoding LDPC CodesACM Transactions on Embedded Computing Systems (TECS), 2014, 13 (4), pp.95. ⟨10.1145/2538668⟩
Article dans une revue
hal-00980616v1
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AFF3CT : Un environnement de simulation pour le codage de canalLe 12ème Colloque du GDR SoC/SiP, Jun 2017, Bordeaux, France. , ⟨10.13140/RG.2.2.13492.91520⟩
Poster de conférence
hal-01965629v1
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An LCF-ADC Model Using Co-simulation Technique2011 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design and IEEE 2011 ADC Forum, Jun 2011, Orvieto, Italy. pp.104-108
Communication dans un congrès
hal-00957286v1
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High-throughput multi-core LDPC decoders based on x86 processorIEEE Transactions on Parallel and Distributed Systems, 2015
Article dans une revue
hal-01286270v1
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Hardware complexity reduction of LDPC-CC decoders based on message-passing approaches2016 17th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA), Dec 2016, Sousse, France. ⟨10.1109/STA.2016.7952003⟩
Communication dans un congrès
hal-01699161v1
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