Number of documents

68

Mon CV


Journal articles7 documents

  • Ming Tang, Zhipeng Guo, Annelie Heuser, Ren Yanzhen, Jie Li, et al.. PFD - A Flexible Higher-Order Masking Scheme. IEEE Trans. on CAD of Integrated Circuits and Systems, 2016. ⟨hal-01629883⟩
  • Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yuichi Hayashi, Naofumi Homma, et al.. Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. IEICE Transactions on Electronics, Institute of Electronics, Information and Communication Engineers, 2014, E97.C (4), pp. 272-279. ⟨hal-01540373⟩
  • Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst, Cédric Murdica, David Naccache. A synthesis of side-channel attacks on elliptic curve cryptography in smart-cards. Journal of Cryptographic Engineering, Springer, 2013, 3 (4), pp.241-265. ⟨10.1007/s13389-013-0062-6⟩. ⟨hal-00934333⟩
  • Frédéric Guilloud, Emmanuel Boutillon, Jacky Tousch, Jean-Luc Danger. Generic description and synthesis of LDPC decoder. IEEE Transactions on Communications, Institute of Electrical and Electronics Engineers, 2007, Vol. 55 (n°11), pp 2084 - 2091. ⟨hal-00347642⟩
  • Frédéric Guilloud, Emmanuel Boutillon, Jacky Tousch, Jean-Luc Danger. Generic description and synthesis of LDPC decoders. IEEE Transactions on Communications, Institute of Electrical and Electronics Engineers, 2007, 55 (11), pp.2084 - 2091. ⟨10.1109/TCOMM.2007.908517⟩. ⟨hal-01859466⟩
  • Frédéric Guillou, Emmanuel Boutillon, Jacky Tousch, Jean-Luc Danger. Generic description and synthesis of LDPC decoder. IEEE Transactions on Communications, Institute of Electrical and Electronics Engineers, 2006. ⟨hal-00105435⟩
  • Emmanuel Boutillon, Jean-Luc Danger, A. Gazel. Design of High Speed AWGN Communication Channel Emulator. Analog Integrated Circuits and Signal Processing, Springer Verlag, 2003, 34, N°2, p133-142. ⟨hal-00105234⟩

Conference papers50 documents

  • Jean-Luc Danger, Adrien Facon, Sylvain Guilley, Karine Heydemann, Ulrich Kühne, et al.. CCFI-Cache: A Transparent and Flexible Hardware Protection for Code and Control-Flow Integrity. 2018 21st Euromicro Conference on Digital System Design (DSD), Aug 2018, Prague, Czech Republic. pp.529-536, ⟨10.1109/DSD.2018.00093⟩. ⟨hal-01900361⟩
  • Margaux Dugardin, Sylvain Guilley, Jean-Luc Danger, Zakaria Najm, Olivier Rioul. Correlated Extra-Reductions Defeat Blinded Regular Exponentiation. Cryptographic Hardware and Embedded Systems – CHES 2016, Aug 2016, Santa Barbara, United States. pp.Pages 3-22. ⟨hal-01362463⟩
  • Margaux Dugardin, Papachristodoulou Louiza, Zakaria Najm, Lejla Batina, Jean-Luc Danger, et al.. Dismantling Real-World ECC with Horizontal and Vertical Template Attacks. Constructive Side-Channel Analysis and Secure Design - COSADE 2016, Apr 2016, Graz, Austria. pp 88-108. ⟨hal-01362466⟩
  • Lionel Rivière, Zakaria Najm, Pablo Rauzy, Jean-Luc Danger, Julien Bringer, et al.. High Precision Fault Injections on the Instruction Cache of ARMv7-M Architectures. HOST 2015: IEEE International Symposium on Hardware-Oriented Security and Trust, May 2015, Washington, United States. ⟨10.1109/HST.2015.7140238⟩. ⟨hal-01208378⟩
  • Xuan Thuy Ngo, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm, Olivier Emery. Hardware property checker for run-time Hardware Trojan detection. Euromicro Conference on Digital System Design (DSD) 2015, Aug 2015, Trondheim, Norway. ⟨10.1109/ECCTD.2015.7300085⟩. ⟨hal-01240226⟩
  • Xuan Thuy Ngo, Zakaria Najm, Shivam Bhasin, Debapriya Basu, Jean-Luc Danger, et al.. Integrated Sensor: A Backdoor for Hardware Trojan Insertions?. Euromicro Conference on Digital System Design (DSD) 2015, Aug 2015, Funchal, Portugal. ⟨10.1109/DSD.2015.119⟩. ⟨hal-01240221⟩
  • Viktor Fischer, Lilian Bossuet, Jean-Luc Danger. Underneath the FPGA Clothes: Enhancing Security: FPL TUTORIAL. 25th International Conference Field Programmable Logic and Applications, FPL 2015, Sep 2015, Londre, United Kingdom. ⟨hal-01279193⟩
  • Xuan Thuy Ngo, Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm. Linear complementary dual code improvement to strengthen encoded circuit against hardware Trojan horses. IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2015, May 2015, McLean, United States. ⟨10.1109/HST.2015.7140242⟩. ⟨hal-01240228⟩
  • Henitsoa Rakotomalala, Xuan Thuy Ngo, Zakaria Najm, Jean-Luc Danger, Sylvain Guilley. Private Circuits II versus Fault Injection Attacks. Reconfig 2015, Dec 2015, Mayan Riviera, Mexico. ⟨hal-01240244⟩
  • Jean-Michel Cioranesco, Jean-Luc Danger, Tarik Graba, Sylvain Guilley, Yves Mathieu, et al.. Cryptographically secure shields. HOST 2014 - IEEE International Symposium on Hardware-Oriented Security and Trust, May 2014, Washington, United States. pp.25 - 31, ⟨10.1109/HST.2014.6855563⟩. ⟨hal-01110463⟩
  • Yuto Nakano, Youssef Souissi, Robert Nguyen, Laurent Sauvage, Jean-Luc Danger, et al.. A Pre-processing Composition for Secret Key Recovery on Android Smartphone. 8th IFIP International Workshop on Information Security Theory and Practice (WISTP), Jun 2014, Heraklion, Crete, Greece. pp.76-91, ⟨10.1007/978-3-662-43826-8_6⟩. ⟨hal-01400921⟩
  • Xuan Thuy Ngo, Zakaria Najm, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger. Method Taking into Account Process Dispersions to Detect Hardware Trojan Horse by Side-Channel. PROOFS: Security Proofs for Embedded Systems 2014, Sep 2014, BUSAN, South Korea. ⟨hal-01240241⟩
  • Michaël Timbert, Jean-Luc Danger, Sylvain Guilley, Thibault Porteboeuf, Florian Praden. HCODE: Hardware-Enhanced Real-Time CFI. PPREW@ACSAC 2014, Dec 2014, New Orleans, United States. ⟨10.1145/2689702.2689708⟩. ⟨hal-01575947⟩
  • Xuan Thuy Ngo, Sylvain Guilley, Shivam Bhasin, Jean-Luc Danger, Zakaria Najm. Encoding the State of Integrated Circuits: a Proactive and Reactive Protection against Hardware Trojans Horses. Workshop on Embedded Systems Security (WESS 2014), Oct 2014, New Delhi, India. ⟨10.1145/2668322.2668329⟩. ⟨hal-01240242⟩
  • Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, et al.. Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. FPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. pp.1--4, ⟨10.1109/FPL.2014.6927422⟩. ⟨hal-01372613⟩
  • Said Hamdioui, Giorgio Di Natale, Battum Van, Jean-Luc Danger, Fethulah Smailbegovic, et al.. Hacking and Protecting IC Hardware. DATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. ⟨10.7873/DATE.2014.112⟩. ⟨lirmm-01234147⟩
  • Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yuichi Hayashi, Naofumi Homma, et al.. On-Chip Power Noise Measurements of Cryptographic VLSI Circuits and Interpretation for Side-Channel Analysis. International Symposium on Electromagnetic Compatibility (EMC Europe), Sep 2013, Brugge, Belgium. pp.405-410. ⟨hal-01215214⟩
  • Zouha Cherif, Jean-Luc Danger, Lilian Bossuet. Evaluation of Delay PUFs on CMOS 65 nm Technology: ASIC vs FPGA. International Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices CryptArchi 2013, Jun 2013, Fréjus, France. ⟨ujm-00840962⟩
  • Zouha Cherif, Jean-Luc Danger, Lilian Bossuet. Evaluation of Delays PUFs on CMOS 65 nm Technology: ASIC vs FPGA. Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, TRUDEVICE 2013, May 2013, Avignon, France. ⟨ujm-00833893⟩
  • Zouha Cherif, Jean-Luc Danger, Florent Lozac'H, Yves Mathieu, Lilian Bossuet. Evaluation of delay PUFs on CMOS 65nm technology: ASIC vs FPGA. International Workshop on Hardware and Architectural Support for Security and Privacy, HASP 2013, Jun 2013, Tel-Aviv, Israel. pp.Article n° 4. ⟨hal-00859079⟩
  • Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Xuan Thuy Ngo, Laurent Sauvage. Hardware Trojan Horses in Cryptographic IP Cores. FDTC (Fault Detection and Tolerance in Cryptography), Aug 2013, Santa Barbara, United States. pp.15-29, ⟨10.1109/FDTC.2013.15⟩. ⟨hal-00855146v2⟩
  • Youssef Souissi, Nicolas Debande, Sami Mekki, Sylvain Guilley, Ali Maalaoui, et al.. On the Optimality of Correlation Power Attack on Embedded Cryptographic Systems. 6th International Workshop on Information Security Theory and Practice (WISTP), Jun 2012, Egham, United Kingdom. pp.169-178, ⟨10.1007/978-3-642-30955-7_15⟩. ⟨hal-01534305⟩
  • Zhoua Cherif Jouini, Jean-Luc Danger, Lilian Bossuet. Physically Unclonable Functions Characterisation. Colloque du GDR SoC-SiP, Jun 2012, Paris, France. ⟨hal-00753222⟩
  • Zhoua Cherif Jouini, Jean-Luc Danger, Sylvain Guilley, Lilian Bossuet. An Easy-to-Design PUF based on a Single Oscillator: the Loop PUF. 15th Euromicro Conference on Digital System Design(DSD), Sep 2012, Cesme, Izmir, Turkey. 7 p. ⟨hal-00753216⟩
  • Endo Sho, Yuichi Hayashi, Naofumi Homma, Takafumi Aoki, Toshihiro Katashita, et al.. Measurement of side-channel information from cryptographic devices on security evaluation platform: Demonstration of SPACES project. SICE Annual Conference, Aug 2012, Akita, Japan. ⟨hal-01540506⟩
  • Sylvain Guilley, Jean-Luc Danger, Robert Nguyen, Philippe Nguyen. System-Level Methods to Prevent Reverse-Engineering, Cloning, and Trojan Insertion. ICISTM, Mar 2012, Grenoble, France. pp.433-438, ⟨10.1007/978-3-642-29166-1_41⟩. ⟨hal-00701990v2⟩
  • Cedric Murdica, Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst, David Naccache. Low-Cost Countermeasure against RPA. CARDIS 2012, Nov 2012, Graz, Austria. pp.106-122. ⟨hal-00799421⟩
  • Maxime Nassar, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger. RSM: a Small and Fast Countermeasure for AES, Secure against 1st and 2nd-order Zero-Offset SCAs. Design Automation and Test in Europe, Mar 2012, Desden, Germany. pp.1173-1178. ⟨hal-00666337⟩
  • Cedric Murdica, Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst, David Naccache. Same Values Power Analysis Using Special Points on Elliptic Curves. COSADE 2012 - Third International Workshop Constructive Side-Channel Analysis and Secure Design, May 2012, Darmstadt, Germany. pp.Cédric Murdica, ⟨10.1007/978-3-642-29912-4_14⟩. ⟨hal-00686565⟩
  • Sébastien Briais, Stéphane Caron, Jean-Michel Cioranesco, Jean-Luc Danger, Sylvain Guilley, et al.. 3D Hardware Canaries. CHES 2012 - 14th International Workshop Cryptographic Hardware and Embedded Systems, Sep 2012, Leuven, Belgium. pp.1-22, ⟨10.1007/978-3-642-33027-8_1⟩. ⟨hal-01111533⟩
  • Sébastien Briais, Jean-Michel Cioranesco, Jean-Luc Danger, Sylvain Guilley, David Naccache, et al.. Random Active Shield. Fault Diagnosis and Tolerance in Cryptography, Sep 2012, Leuven, Belgium. 11 p., ⟨10.1109/FDTC.2012.11⟩. ⟨hal-00721569v2⟩
  • Zhoua Cherif Jouini, Jean-Luc Danger, Lilian Bossuet. Performance Evaluation of Silicon Physically Unclonable Function by Studing Physicals Values. 9th IEEE International NEWCAS conference 2011, Jun 2011, Bordeaux, France. pp.482-485. ⟨hal-00605720⟩
  • Sylvain Guilley, Olivier Meynard, Maxime Nassar, Guillaume Duc, Philippe Hoogvorst, et al.. Vade Mecum on Side-Channels Attacks and Countermeasures for the Designer and the Evaluator. Design & Technology of Integrated Systems, Apr 2011, Athens, Greece. pp.6, ⟨10.1109/DTIS.2011.5941419⟩. ⟨hal-00579020v2⟩
  • Houssem Maghrebi, Sylvain Guilley, Jean-Luc Danger. Leakage Squeezing Countermeasure against High-Order Attacks. 5th Workshop on Information Security Theory and Practices (WISTP), Jun 2011, Heraklion, Crete, Greece. pp.208-223, ⟨10.1007/978-3-642-21040-2_14⟩. ⟨hal-01573295⟩
  • Sylvain Guilley, Karim Khalfallah, Victor Lomne, Jean-Luc Danger. Formal Framework for the Evaluation of Waveform Resynchronization Algorithms. 5th Workshop on Information Security Theory and Practices (WISTP), Jun 2011, Heraklion, Crete, Greece. pp.100-115, ⟨10.1007/978-3-642-21040-2_7⟩. ⟨hal-01573296⟩
  • Houssem Maghrebi, Sylvain Guilley, Jean-Luc Danger, Florent Flament. Entropy-based Power Attack. Hardware-Oriented Security and Trust, Jun 2010, Anaheim, CA, United States. pp.1-6, ⟨10.1109/HST.2010.5513124⟩. ⟨hal-00618482v2⟩
  • Luc Moreau, Alexis Polti, Jean-Luc Danger, Jean-Marie Nicolas, Renaud Fallourd, et al.. De la roue au radar : quelques innovations en métrologie radar. 5éme Colloque Interdisciplinaire en Instrumentation (C2I), Jan 2010, Le Mans, France. pp.110-118. ⟨halsde-00461037⟩
  • Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane. Fault Injection Resilience. Fault Diagnosis and Tolerance in Cryptography, Aug 2010, Santa Barbara, United States. pp.51-65, ⟨10.1109/FDTC.2010.15⟩. ⟨hal-00482194v9⟩
  • Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Tarik Graba, Jean-Luc Danger. WDDL is Protected Against Setup Time Violation Attacks. CHES, Sep 2009, Lausanne, Switzerland. pp.73-83, ⟨10.1109/FDTC.2009.40⟩. ⟨hal-00410135⟩
  • Houssem Maghrebi, Jean-Luc Danger, Florent Flament, Sylvain Guilley, Laurent Sauvage. Evaluation of Countermeasure Implementations Based on Boolean Masking to Thwart Side-Channel Attacks. SCS, Nov 2009, Jerba, Tunisia. 6 p., ⟨10.1109/ICSCS.2009.5412597⟩. ⟨hal-00425523v4⟩
  • Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, et al.. Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig, Dec 2009, Cancún, Mexico. pp.213 - 218, ⟨10.1109/ReConFig.2009.50⟩. ⟨hal-00411843v3⟩
  • Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar. Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints.. Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09., Apr 2009, NICE, France. pp.640-645. ⟨hal-00325417v3⟩
  • Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu. Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. Secure System Integration and Reliability Improvement, Jul 2008, Yokohama, Japan. pp.16-23, ⟨10.1109/SSIRI.2008.31⟩. ⟨hal-00259153v5⟩
  • Sylvain Guilley, Sumanta Chaudhuri, Laurent Sauvage, Tarik Graba, Jean-Luc Danger, et al.. Shall we trust WDDL?. Future of Trust in Computing, Jun 2008, Berlin, Germany. pp.208-215, ⟨10.1007/978-3-8348-9324-6_22⟩. ⟨hal-00409024⟩
  • Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst. Area Optimization of Cryptographic Co-Processors Implemented in Dual-Rail with Precharge Positive Logic. International Conference on Field Programmable Logic and Applications, Sep 2008, Heidelberg, Germany. pp.161-166, ⟨10.1109/FPL.2008.4629925⟩. ⟨hal-00320425v2⟩
  • Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet. Silicon-level Solutions to Counteract Passive and Active Attacks. FDTC, Aug 2008, Washington, DC, United States. pp.3-17, ⟨10.1109/FDTC.2008.18⟩. ⟨hal-00311431⟩
  • Emmanuel Boutillon, Frédéric Guillou, Jean-Luc Danger. lambda-Min Decoding Algorithm of Regular and Irregular LDPC Codes. 3nd International Symposium on Turbo Codes & Related Topics, 2003, Brest, France. ⟨hal-00068941⟩
  • Frédéric Guilloud, Emmanuel Boutillon, Jean-Luc Danger. Lambda-Min Decoding Algorithm of Regular and Irregular LDPC Codes. 3nd International Symposium on Turbo Codes and Related Topics, Sep 2003, Brest, France. pp.451-454. ⟨hal-00105245⟩
  • Frédéric Guilloud, Emmanuel Boutillon, Jean-Luc Danger. Décodage des codes LDPC par l'algorithme lambda-min. GRETSI 2003, Sep 2003, Paris, France. ⟨hal-00105265⟩
  • Jean-Luc Danger, Adel Ghazel, Emmanuel Boutillon, H. Laamari. Efficient FPGA Implementation of Gaussian Noise Generator for Communication Channel Emulation. 7th IEEE International Conference on Electronicsm Circuits & Systemes (ICECS'2K), Dec 2001, Kaslik, Lebanon. pp.1. ⟨hal-00347213⟩

Poster communications1 document

Books1 document

Book sections3 documents

  • Nicolas Bruneau, Jean-Luc Danger, Adrien Facon, Sylvain Guilley, Soshi Hamaguchi, et al.. Development of the Unified Security Requirements of PUFs During the Standardization Process. Innovative Security Solutions for Information Technology and Communications. 11th International Conference, SecITC 2018, Bucharest, Romania, November 8–9, 2018, Revised Selected Papers, LNCS (11359), Springer, pp.314-330, 2019, 978-3-030-12942-2. ⟨10.1007/978-3-030-12942-2_24⟩. ⟨hal-02265318⟩
  • Eduardo Wanderley, Romain Vaslin, Jérémie Crenne, Pascal Cotret, Jean-Philippe Diguet, et al.. SecurityFPGA Analysis. Security Trends for FPGAS - From Secured to Secure Reconfigurable Systems, pp.7-46, 2011. ⟨lirmm-00809327⟩
  • Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, et al.. Physical Design of FPGA Interconnect to Prevent Information Leakage. Woods, R.; Compton, K.; Bourganis, C.; Diniz, P.C. Reconfigurable Computing: Architecture, Tools, and Applications, 4943, Springer, pp.87-98, 2008, Lecture Notes in Computer Science, ⟨10.1007/978-3-540-78610-8_11⟩. ⟨hal-00299487⟩

Directions of work or proceedings1 document

  • Jean-Luc Danger, Mourad Debbabi, Jean-Yves Marion, Joaquin Garcia-Alfaro, Nur Zincir Heywood. Foundations and practice of security : 6th international symposium, FPS 2013, La Rochelle, France, October 21-22, 2013, revised selected papers. 8352, Springer, pp.444, 2014, Lecture Notes in Computer Science, 978-3-319-05302-8. ⟨hal-01264784⟩

Preprints, Working Papers, ...4 documents

  • Jean-Luc Danger, Sylvain Guilley, Shivam Bhasin, Maxime Nassar, Laurent Sauvage. Overview of Dual Rail with Precharge Logic Styles to Thwart Implementation-Level Attacks on Hardware Cryptoprocessors. 2009. ⟨hal-00431261⟩
  • Sami Mekki, Jean-Luc Danger, Benoit Miscopein, Joseph J. Boutros. Chi-squared Distribution Approximation for Probabilistic Energy Equalizer Implementation in Impulse-Radio UWB Receiver. 2008. ⟨hal-00299912⟩
  • Sami Mekki, Jean-Luc Danger, Benoit Miscopein, Joseph J. Boutros. EM Channel Estimation in a Low-cost UWB Receiver based on Energy Detection. 2008. ⟨hal-00296575⟩
  • Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar. Successful Attack on an FPGA-based Automatically Placed and Routed WDDL+ Crypto Processor.. 2008. ⟨hal-00339858⟩

Reports1 document

  • Jean-Luc Danger, Sylvain Guilley, Philippe Hoogvorst, Cédric Murdica, David Naccache. Dynamic Countermeasure Against the Zero Power Analysis. [Research Report] IACR Cryptology ePrint Archive 2013: 764 (2013), 2013. ⟨hal-00934336⟩