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Number of documents

9

Research engineer in memory circuit design


Journal articles1 document

  • Reda Boumchedda, Jean-Philippe Noel, Bastien Giraud, Kaya Can Akyel, Mélanie Brocard, et al.. High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2017, 25 (8), pp.2296-2306. ⟨10.1109/TVLSI.2017.2688862⟩. ⟨cea-02193602⟩

Conference papers6 documents

  • Ian O'Connor, Mayeul Cantan, Cedric Marchand, Bertrand Vilquin, Bastien Giraud, et al.. Prospects for energy-efficient edge computing with integrated HfO 2-based ferroelectric devices. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC), Oct 2018, Verona, Italy. ⟨10.1109/VLSI-SoC.2018.8644809⟩. ⟨hal-01916992⟩
  • Maha Kooli, Henri-Pierre Charles, Clément Touzet, Bastien Giraud, Jean-Philippe Noel. Smart Instruction Codes for In-Memory Computing Architectures Compatible with Standard SRAM Interfaces. Design, Automation and Test in Europe, Mar 2018, Dresde, Germany. ⟨cea-01757656⟩
  • Maha Kooli, Henri-Pierre Charles, Clément Touzet, Bastien Giraud, Jean-Philippe Noel. Software Platform Dedicated for In-Memory Computing Circuit Evaluation. RSP'17 (Rapid System Prototyping), Oct 2017, Séoul, South Korea. ⟨10.1145/3130265.3130322⟩. ⟨cea-01625320⟩
  • Alexandre Levisse, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau, Jean-Michel Portal. Capacitor based SneakPath compensation circuit for transistor-less ReRAM architectures. Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Jul 2016, Beijing, China. pp.7-12, ⟨10.1145/2950067.2950073⟩. ⟨hal-01435118⟩
  • Kaya Can Akyel, Henri-Pierre Charles, Julien Mottin, Bastien Giraud, Suraci Grégory, et al.. DRC 2 : Dynamically Reconfigurable Computing Circuit based on Memory Architecture. IEEE International Conference on Rebooting Computing, Oct 2016, San Diego, France. ⟨cea-01376554⟩
  • Alexandre Levisse, Bastien Giraud, Jean-Philippe Noel, Mathieu Moreau, Jean-Michel Portal. SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures. 2015 15th Non-Volatile Memory Technology Symposium (NVMTS), Oct 2015, Beijing, China. ⟨10.1109/NVMTS.2015.7457426⟩. ⟨hal-01745689⟩

Other publications1 document

  • Henri-Pierre Charles, Maha Kooli, Clément Touzet, Bastien Giraud, Jean-Philippe Noel. Smart Instruction Codes For In-Memory Computing Architectures Compatible With Standard Sram Interfaces. 2018. ⟨cea-01757665⟩

Theses1 document

  • Jean-Philippe Noël. Optimisation de dispositifs FDSOI pour la gestion de la consommation et de la vitesse : application aux mémoires et fonctions logiques. Autre. Université de Grenoble, 2011. Français. ⟨NNT : 2011GRENT069⟩. ⟨tel-00701765v2⟩