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5 résultats
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Optimizations for an efficient reconfiguration of an ASIP-based turbo decoderISCAS 2013 : IEEE International Symposium on Circuits and Systems, May 2013, Beijing, Chine. pp.493 - 496, ⟨10.1109/ISCAS.2013.6571888⟩
Communication dans un congrès
hal-00873979v1
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FPGA Prototyping and Performance Evaluation of Multi-standard Turbo/LDPC Encoding and DecodingRSP 2012: IEEE International Symposium on Rapid System Prototyping, Oct 2012, Tampere, Finland
Communication dans un congrès
hal-00797561v1
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Flexible Multi-ASIP SoC for Turbo/LDPC DecoderSOC-SIP : colloque national du groupe de recherches System On Chip - System In Package, Jun 2012, Paris, France
Communication dans un congrès
hal-00725184v1
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A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIPISVLSI 2013 : IEEE Computer Society Annual Symposium on VLSI, Aug 2013, Natal, Brazil. ⟨10.1109/ISVLSI.2013.6654620⟩
Communication dans un congrès
hal-01002828v1
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Efficient dynamic configuration of a multi-ASIP turbo decoderGDR SoC-SiP 2013 : Colloque National du Groupe de Recherche System on Chip -System in Package, Jun 2013, Lyon, France
Poster de conférence
hal-00876017v1
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