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136 résultats
High density emerging resistive memories: What are the limits?2017 IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), Feb 2017, Bariloche, Argentina. ⟨10.1109/LASCAS.2017.7948104⟩
Communication dans un congrès
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Development of a CMOS oscillator chain for particle detection based on SOI technology2015 4th International Conference on Advancements in Nuclear Instrumentation Measurement Methods and their Applications (ANIMMA), Apr 2015, Lisbon, France. pp.1-5
Communication dans un congrès
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Fate of coagulant species and conformational effects during the aggregation of a model of a humic substance with Al13 polycationsWater Research, 2006, 40 (10), pp.1965-1974. ⟨10.1016/j.watres.2006.03.014⟩
Article dans une revue
istex
hal-02265622v1
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1TBulk eDRAM Using Gate-Induced Drain-Leakage (GIDL) Current for High Speed and Low Power applicationsInternational conference on Solid State Devices and Materials (SSDM), Sep 2008, Ibaraki, Japan
Communication dans un congrès
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A tunneling model for gate oxide failure in deep sub-micron technologypp.1404-1405, 2004, Design, Automation and Test in Europe Conference and Exhibition, Vols 1 and 2, Proceedings, 0-7695-2085-5
Ouvrages
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GOSMOS: A Gate Oxide Short Defect Embedded in a MOS Compact ModelLATW: Latin American Test Workshop, Feb 2003, Natal, Brazil
Communication dans un congrès
lirmm-00269604v1
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Self-rectifying Behavior and Analog Switching Under Identical Pulses Using Tri-layer RRAM Crossbar Array for Neuromorphic Systems2017 IEEE 9TH INTERNATIONAL MEMORY WORKSHOP (IMW), 2017, Unknown, Unknown Region. pp.141-144
Communication dans un congrès
hal-01694462v1
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Self-Rectifying Behavior and Analog Switching under Identical Pulses Using Tri-Layer RRAM Crossbar Array for Neuromorphic Systems2017 IEEE International Memory Workshop (IMW), May 2017, Monterey, United States. ⟨10.1109/IMW.2017.7939102⟩
Communication dans un congrès
hal-01788143v1
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PCM compact model: Optimized methodology for model card extraction2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sep 2018, Austin, United States. pp.190-193, ⟨10.1109/SISPAD.2018.8551654⟩
Communication dans un congrès
cea-02188521v1
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Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction15th IEEE / ACM International Symposium on Nanoscale Architectures (NANOARCH), Jul 2019, Qingdao, China
Communication dans un congrès
hal-02399718v1
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SneakPath compensation circuit for programming and read operations in RRAM-based CrossPoint architectures2015 15th Non-Volatile Memory Technology Symposium (NVMTS), Oct 2015, Beijing, China. ⟨10.1109/NVMTS.2015.7457426⟩
Communication dans un congrès
hal-01745689v1
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Impact of SEU configurations on a SRAM cell response at circuit level2011 12th Latin American Test Workshop - LATW, Mar 2011, Beach of Porto de Galinhas, France. pp.1-5
Communication dans un congrès
hal-02025647v1
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Investigation of a CMOS oscillator concept for particle detection and diagnosis2012 13th Latin American Test Workshop - LATW, Apr 2012, Quito, France. pp.1-5
Communication dans un congrès
hal-02025655v1
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Electromagnetic Analysis Perturbation using Chaos GeneratorTruedevice 2016, Nov 2016, Barcelona, Spain
Communication dans un congrès
hal-01455446v1
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A new method for test chip and single 40nm NOR Flash cell electrical parameters correlation using a CAST structure2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Apr 2018, Hsinchu, Taiwan. ⟨10.1109/VLSI-TSA.2018.8403859⟩
Communication dans un congrès
hal-01900783v1
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Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM BridgesESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), Sep 2021, Grenoble, France. pp.83-86, ⟨10.1109/ESSCIRC53450.2021.9567742⟩
Communication dans un congrès
hal-03597353v1
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Digital Biologically Plausible Implementation of Binarized Neural Networks With Differential Hafnium Oxide Resistive Memory ArraysFrontiers in Neuroscience, 2020, 13, ⟨10.3389/fnins.2019.01383⟩
Article dans une revue
hal-02436382v1
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Binary ReRAM-based BNN first-layer implementation2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Apr 2023, Antwerp, Belgium. pp.1-6, ⟨10.23919/DATE56975.2023.10137057⟩
Communication dans un congrès
hal-04270562v1
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Optimization of SEU Simulations for SRAM Cells Reliability under RadiationJournal of Electronic Testing: : Theory and Applications, 2012, 28 (3), pp.331-338
Article dans une revue
hal-02025257v1
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SITARe: A simulation tool for analysis and diagnosis of radiation effects2012 13th Latin American Test Workshop - LATW, Apr 2012, Quito, France. pp.1-5
Communication dans un congrès
hal-02030884v1
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Comparison of a readout chain dedicated to the signal conditioning of a particle detector and an innovative chain based on a VCO concept15. European Conference on Radiation and Its Effects on Components and Systems (Radecs), Sep 2015, Moscou, Russia
Communication dans un congrès
hal-01594142v1
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A Built-In Self-Test Structure (BIST) for Resistive RAMs Characterization: Application to Bipolar OxRRAMSolid-State Electronics, 2015, 103, pp.73 - 78. ⟨10.1016/j.sse.2014.09.005⟩
Article dans une revue
hal-01737300v1
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Built-in tuning of the local oscillator for open loop modulation of low cost, low power RF transceiver2013 14th Latin American Test Workshop - LATW, Apr 2013, Cordoba, Argentina. ⟨10.1109/LATW.2013.6562686⟩
Communication dans un congrès
hal-01895505v1
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Capacitor based SneakPath compensation circuit for transistor-less ReRAM architecturesProceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Jul 2016, Beijing, China. pp.7-12, ⟨10.1145/2950067.2950073⟩
Communication dans un congrès
hal-01435118v1
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High voltage recycling scheme to improve power consumption of regulated charge pumps2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sep 2017, Thessaloniki, Greece. ⟨10.1109/PATMOS.2017.8106995⟩
Communication dans un congrès
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Switching Event Detection and Self-Termination Programming Circuit for Energy Efficient ReRAM Memory ArraysIEEE Transactions on Circuits and Systems II: Express Briefs, 2019, 66 (5), pp.748-752. ⟨10.1109/TCSII.2019.2908967⟩
Article dans une revue
hal-02158840v1
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Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching MemoriesIEEE Transactions on Circuits and Systems I: Regular Papers, 2014, 61 (2), pp.443 - 454. ⟨10.1109/TCSI.2013.2278332⟩
Article dans une revue
hal-01743999v1
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Resistive RAM variability monitoring using a ring oscillator based test chipMicroelectronics Reliability, 2016, 64 (SI), pp.59-62. ⟨10.1016/j.microrel.2016.07.097⟩
Article dans une revue
hal-01434980v1
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MM11 Based Flash Memory Cell Model Including Characterization ProcedureIEEE International Symposium on Circuits and Systems, May 2006, Ile de Kos, Greece. pp.3518-3521
Communication dans un congrès
hal-00525036v1
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Thin film embedded memory solutionsCurrent Applied Physics, 2010, 10 (1, suppl.1), pp.e9-e12
Article dans une revue
hal-00519276v1
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