Nombre de documents

73

CV de Jean-Max Dutertre


Communication dans un congrès57 documents

  • Raphael Viera, Rodrigo Possamai Bastos, Jean-Max Dutertre, Olivier Potin, Marie-Lise Flottes, et al.. Validation Of Single BBICS Architecture In Detecting Multiple Faults. ATS: Asian Test Symposium, Nov 2015, Mumbai, India. 24th IEEE Asian Test Symposium. <https://www.ee.iitb.ac.in/ats15/>. <lirmm-01234067>
  • Raphael Viera, Rodrigo Possamai Bastos, Jean-Max Dutertre, Olivier Potin, Marie-Lise Flottes, et al.. Evaluation of Bulk Built-In Current Sensors Detecting Multiple Transient Faults. ATS: Asian Test Symposium, Nov 2015, Bombay, India. IEEE, IEEE Asian Test Symposium, 2015. <hal-01414752>
  • N Borrel, C Champeix, M Lisart, A Sarafianos, E Kussener, et al.. Electrical model of an NMOS body biased structure in triple-well technology under photoelectric laser stimulation. Reliability Physics Symposium (IRPS), 2015 IEEE International, Apr 2015, Monterey, United States. <10.1109/IRPS.2015.7112799>. <emse-01230163>
  • Nicolas Borrel, Clément Champeix, Edith Kussener, Wenceslas Rahajandraibe, M. Lisart, et al.. Influence of triple-well technology on laser fault injection and laser sensor efficiency. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on, Apr 2015, Monterey, United States. <10.1109/DFT.2015.7315141>. <emse-01230166>
  • Marc Lacruche, Nicolas Borrel, Clément Champeix, C. Roscian, A. Sarafianos, et al.. Laser Fault Injection into SRAM cells: Picosecond versus Nanosecond pulses. On-Line Testing Symposium (IOLTS), 2015 IEEE 21st International, Jul 2015, Halkidiki, France. <10.1109/IOLTS.2015.7229820>. <emse-01227286>
  • Clément Champeix, Nicolas Borrel, Jean-Max Dutertre, Bruno Robisson, Mathieu Lisart, et al.. SEU sensitivity and modeling using picosecond pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2015 IEEE International Symposium on, Oct 2015, Amherst, United States. <10.1109/DFT.2015.7315158>. <emse-01227355v2>
  • Clément Champeix, Nicolas Borrel, Jean-Max Dutertre, Bruno Robisson, Mathieu Lisart, et al.. Experimental validation of a Bulk Built-In Current Sensor for detecting laser-induced currents. On-Line Testing Symposium (IOLTS), 2015 IEEE 21st International, Jul 2015, Halkidiki, Greece. <10.1109/IOLTS.2015.7229849>. <emse-01227307>
  • Stephan De Castro, Jean-Max Dutertre, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. Figure of merits of 28nm Si technologies for implementing laser attack resistant security dedicated circuits. ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Jul 2015, Montpellier, France. 2015, Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). <10.1109/ISVLSI.2015.76>. <emse-01227138>
  • Loïc Zussa, Jean-Max Dutertre, Jessy Clédière, Bruno Robisson. Analysis of a fault injection mechanism related to voltage glitches using an on-chip voltmeter. TRUDEVICE Workshop (colocated with ETS 2014), May 2014, Paderborn, Germany. 2014. <emse-01099039>
  • Loic Zussa, Jean-Max Dutertre, Jessy Clediere, Bruno Robisson. Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter. IEEE Int. Symposium on Hardware-Oriented Security and Trust (HOST), May 2014, Arlington, France. <10.1109/HST.2014.6855583>. <emse-01099010>
  • Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre, et al.. Laser-Induced Fault Effects in Security-Dedicated Circuits. Luc Claesen; Maria-Teresa Sanz-Pascual; Ricardo Reis; Arturo Sarmiento-Reyes. VLSI-SoC: Very Large Scale Integration - System on a Chip, Oct 2014, Playa del Carmen, Mexico. 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration - System on a Chip, AICT-464, pp.220-240, 2015, IFIP Advances in Information and Communication Technology. <10.1007/978-3-319-25279-7_12>. <hal-01383737>
  • Paolo Maistri, Regis Leveugle, Lilian Bossuet, Alain Aubert, Viktor Fischer, et al.. ElectroMagnetic Analysis and Fault Injection onto Secure Circuits. VLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2014, Mexico, Mexico. 22nd International Conference on Very Large Scale Integration, 2014, <10.1109/VLSI-SoC.2014.7004182>. <emse-01099025>
  • Regis Leveugle, Paolo Maistri, Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, et al.. Laser-induced Fault Effects in Security-dedicated Circuits. International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2014, Mexico, Mexico. <emse-01099022>
  • Rodrigo Possamai Bastos, Jean-Max Dutertre, Frank Sill Torres. Comparison of bulk built-in current sensors in terms of transient-fault detection sensitivity. CMOS variability (VARI), Sep 2014, Palma de Mallorca, Spain. <10.1109/VARI.2014.6957089>. <emse-01099015>
  • Jean-Max Dutertre, Stephan De Castro, Alexandre Sarafianos, Noémie Boher, Bruno Rouzeyre, et al.. Laser attacks on integrated circuits: from CMOS to FD-SOI. DTIS: Design and Technology of Integrated Systems, May 2014, Santorin, Greece. 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014, <10.1109/DTIS.2014.6850664>. <emse-01099042>
  • Nicolas Borrel, Clément Champeix, Mathieu Lisart, Alexandre Sarafianos, Edith Kussener, et al.. Characterization and simulation of a body biased structure in triple-well technology under pulsed photoelectric laser stimulation. International Symposium for Testing and Failure Analysis (ISTFA), Nov 2014, Houston, United States. <emse-01099035>
  • Loic Zussa, Amine Dehbaoui, Karim Tobich, Jean-Max Dutertre, Philippe Maurine, et al.. Efficiency of a glitch detector against electromagnetic fault injection. DATE: Design, Automation and Test in Europe, Mar 2014, Dresden, Germany. IEEE, pp.1-6, 2014, Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014. <10.7873/DATE.2014.216>. <lirmm-01096047>
  • Sébastien Ordas, Ludovic Guillaume-Sage, Karim Tobich, Jean-Max Dutertre, Philippe Maurine. Evidence of a larger EM-induced fault model. CARDIS: Smart Card Research and Advanced Application, Nov 2014, Paris, France. 13th Smart Card Research and Advanced Application Conference, LNCS (8968), pp.245-259, 2015, Smart Card Research and Advanced Applications. <http://cedric.cnam.fr/events/cardis/>. <10.1007/978-3-319-16763-3_15>. <emse-01099037>
  • Bruno Robisson, Ingrid Exurville, Jean-Yves Zie, Hélène Le Bouder, Jean-Max Dutertre, et al.. The bad and the good of physical functions. Cryptarchi, Jun 2013, Fréjus, France. 2013. <cea-01094232>
  • Amine Dehbaoui, Jean-Max Dutertre, Bruno Robisson, Assia Tria. Investigation of Near-Field Pulsed EMI at IC Level. Asia-Pacific International Symposium and Exhibition on Electromagnetic Compatibility, May 2013, Melbourne, Australia. <cea-01097120>
  • Loïc Zussa, Jean-Max Dutertre, Jessy Clédière, Assia Tria. From physical stresses to timing constraints violation. Forth International Workshop on Constructive Side-Channel Analysis and Secure Design, COSADE 2013, Mar 2013, Paris, France. <emse-01110353>
  • Loïc Zussa, Jean-Max Dutertre, Jessy Clédière, Assia Tria. Power supply glitch induced faults on FPGA: an in-depth analysis of the injection mechanism. On-Line Testing Symposium (IOLTS), 2013 IEEE 19th International, Jul 2013, Chania, Greece. <10.1109/IOLTS.2013.6604060>. <emse-01109131>
  • Amine Dehbaoui, Amir-Pasha Mirbaha, Nicolas Moro, Jean-Max Dutertre, Assia Tria. Electromagnetic glitch on the AES round counter. Springer Berlin Heidelberg. Fourth International Workshop on Constructive Side-Channel Analysis and Secure Design - COSADE'2013, Mar 2013, Paris, France. Springer Berlin Heidelberg, Lecture Notes in Computer Science (7864), pp 17-31, 2013, Lecture Notes in Computer Science. <10.1007/978-3-642-40026-1>. <emse-00837514>
  • Alexandre Sarafianos, Mathieu Lisart, Olivier Gagliano, Valérie Serradeil, Cyril Roscian, et al.. Robustness improvement of an SRAM cell against laser-induced fault injection. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on, Oct 2013, New York, United States. <10.1109/DFT.2013.6653598>. <emse-01109141>
  • Cyril Roscian, Alexandre Sarafianos, Jean-Max Dutertre, Assia Tria, Mathieu Lisart. Discussion on the Model of Laser Induced Faults in SRAM Memory cells. Forth International Workshop on Constructive Side-Channel Analysis and Secure Design, COSADE 2013, Mar 2013, Paris, France. 2013. <emse-01109302>
  • Amir-Pasha Mirbaha, Jean-Max Dutertre, Assia Tria. Differential Analysis of Round-Reduced AES Faulty Ciphertexts. Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 IEEE International Symposium on, Oct 2013, New York, United States. <10.1109/DFT.2013.6653607>. <emse-01109144>
  • Jean-Max Dutertre, Cyril Roscian, Alexandre Sarafianos, Marc Lacruche. Laser-Induced Faults in SRAM Memory Cells: Experimental Results and Simulation-based Analysis. TRUDEVICE - WG Meetings, 2013, Dec 2013, Freiburg, Germany. <emse-01110358>
  • Cyril Roscian, Jean-Max Dutertre, Assia Tria. Frontside Laser Fault Injection on Cryptosystems – Application to the AES' last round. Hardware-Oriented Security and Trust (HOST), 2013 IEEE International Symposium on, Jun 2013, Austin, United States. <10.1109/HST.2013.6581576>. <emse-01109128>
  • Alexandre Sarafianos, Olivier Gagliano, Valérie Serradeil, Mathieu Lisart, Jean-Max Dutertre, et al.. Building the electrical model of the pulsed photoelectric laser stimulation of an NMOS transistor in 90nm technology. International Reliability Physics Symposium (IRPS), Apr 2013, Monterey, United States. 2013, <10.1109/IRPS.2013.6532028>. <emse-01109124>
  • Cyril Roscian, Alexandre Sarafianos, Jean-Max Dutertre, Assia Tria. Fault Model Analysis of Laser-Induced Faults in SRAM Memory Cells. Fault Diagnosis and Tolerance in Cryptography (FDTC), 2013 Workshop on, Aug 2013, Santa-Barbara, United States. <10.1109/FDTC.2013.17>. <emse-01109133>
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. ESREF: European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Sep 2013, Arcachon, France. IEEE Computer Society, 24th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, pp.B3c-2 #68, 2013. <hal-00872705>
  • Rodrigo Possamai Bastos, Frank Sill Torres, Jean-Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, et al.. A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults. PATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2013, Karlsruhe, Germany. 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, pp.157-163, 2013, <http://www.patmos-conf.org/>. <10.1109/PATMOS.2013.6662169>. <lirmm-00968621>
  • Philippe Maurine, Amine Dehbaoui, François Poucheret, Jean-Max Dutertre, Bruno Robisson, et al.. On the use of the EM medium as a fault injection means. CryptArch: Cryptographic Architectures Embedded in Reconfigurable Devices, Jun 2012, Fréjus, France. 10th International Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices (CrypArchi 2012), 2012. <emse-00742707>
  • Bruno Robisson, Hélène Le Bouder, Jean-Max Dutertre, Assia Tria. A unified formalism for side-channel and fault attacks on cryptographic circuits. 27th Conference on Design of Circuits and Integrated Systems (DCIS), Nov 2012, Avignon, France. <emse-00742510>
  • Ronan Lashermes, Guillaume Reymond, Jean-Max Dutertre, Jacques Fournier, Bruno Robisson, et al.. A DFA on AES based on the entropy of error distributions. FDTC 2012, Sep 2012, Leuven, Belgium. pp.34, 2012. <emse-00742642>
  • Alexandre Sarafianos, R. Llido, Olivier Gagliano, Valérie Serradeil, V. Goubier, et al.. Characterization and TCAD simulation of 90 nm technology transistors under continuous photoelectric laser stimulation for failure analysis improvement. 19th IEEE INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS, Jul 2012, Singapore, Singapore. pp.1-6, 2012. <emse-00742705>
  • Loïc Zussa, Jean-Max Dutertre, Jessy Clédière, Bruno Robisson, Assia Tria. Investigation of timing constraints violation as a fault injection means. 27th Conference on Design of Circuits and Integrated Systems (DCIS), Nov 2012, Avignon, France. pas encore paru, 2012. <emse-00742652>
  • Amine Dehbaoui, Jean-Max Dutertre, Bruno Robisson, Assia Tria. Electromagnetic Transient Faults Injection on a hardware and software implementations of AES. FDTC 2012, Sep 2012, Leuven, Belgium. pp.7, 2012. <emse-00742639>
  • Jean-Max Dutertre, Amir Pasha Mirbaha, David Naccache, Anne-Lise Ribotta, Assia Tria, et al.. Fault Round Modification Analysis of the Advanced Encryption Standard. Hardware-Oriented Security and Trust (HOST), 2012, Jun 2012, San Francisco, United States. IEEE, pp.140--145, 2002, <10.1109/HST.2012.6224334>. <emse-00742567>
  • R Llido, A Sarafianos, O Gagliano, V Serradeil, V Goubier, et al.. Characterization and TCAD Simulation of 90nm Technology PMOS Transistor Under Continuous Photoelectric Laser Stimulation for Failure Analysis Improvement. 38th International Symposium for Testing and Failure Analysis, ISTFA 2012, Nov 2012, Phoenix, United States. <emse-01130626>
  • Sarafianos Alexandre, R. Llido, Jean-Max Dutertre, Olivier Gagliano, Valérie Serradeil, et al.. Building the electricalmodel of the PhotoelectricLaserStimulation of a NMOS transistor in 90 nm technology. 38th International Symposium for Testing and Failure Analysis, Nov 2012, Phoenix, United States. pas encore paru, 2012. <emse-00742629>
  • A Sarafianos, R Llido, O Gagliano, V Serradeil, Mathieu Lisart, et al.. Building the electrical model of the pulsed photoelectric laser stimulation of an NMOS transistor in 90nm technology. 38th International Symposium for Testing and Failure Analysis, ISTFA 2012, Nov 2012, Phoenix, United States. <emse-01130636>
  • Paolo Maistri, Sébastien Tiran, Amine Dehbaoui, Philippe Maurine, Jean-Max Dutertre. Countermeasures against EM Analysis. 10th CryptArchi Workshop - St-Etienne Goutelas 2012, Jun 2012, Saint-Etienne, France. <emse-01130646>
  • Jean-Max Dutertre, Jacques Fournier, Amir Pasha Mirbaha, David Naccache, Jean-Baptiste Rigaud, et al.. Review of fault injection mechanisms and consequences on countermeasures design. Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2011 6th International Conference on, Apr 2011, athens, Greece. pp.1 - 6, 2011, <10.1109/DTIS.2011.5941421>. <emse-00623133>
  • Jacques Jean-Alain Fournier, Doulcier Marion, Jean-Max Dutertre, Jean-Baptiste Rigaud, Bruno Robisson, et al.. A Side-Channel and Fault-Attack Resistant AES Circuit Working on Duplicated Complemented Values. International Solid State Circuits Conference - ISSCC 2011, Feb 2011, San Francisco, United States. pp.15.6, 2012. <emse-00541009>
  • Michel Agoyan, Sylvain Bouquet, Marion Doulcier-Verdier, Jean-Max Dutertre, Jacques Fournier, et al.. Design of a duplicated fault-detecting AES chip and yet using clock set-up time violations to extract 13 out of 16 bytes of the secret key. Smart Systems Integration, Mar 2011, Dresden, Germany. pp.00, 2011. <emse-00625679>
  • Jean-Baptiste Rigaud, Jean-Max Dutertre, Michel Agoyan, Bruno Robisson, Assia Tria. Experimental Fault Injection around the Prototyping of an AES Cryptosystem. Reconfigurable Communication-centric Systems on Chip 2010, May 2010, karlsruhe, Germany. <emse-00505355>
  • Jean-Max Dutertre, Amir-Pasha Mirbaha, David Naccache, Assia Tria. Reproducible Single-Byte Laser Fault Injection. 6th Conference on Ph.D. Research in Microelectronics & Electronics, PRIME 2010, Jul 2010, Berlin, Germany. <emse-01130782>
  • Michel Agoyan, Jean-Max Dutertre, David Naccache, Bruno Robisson, Assia Tria. When Clocks Fail: On Critical Paths and Clock Faults. Springer Verlag. 9th IFIP WG 8.1/11.2 International conference, CARDIS 2010, Apr 2010, Passau, Germany. Springer Verlag, pp.182-193, 2010, Lecture Notes in Computer Science. <10.1007/978-3-642-12510-2_13>. <emse-00474337>
  • Amir Pasha Mirbaha, Jean-Max Dutertre, Anne-Lise Ribotta, Michel Agoyan, Assia Tria, et al.. Single-Bit DFA Using Multiple-Byte Laser Fault Injection.. 10th IEEE International Conference on Technologies for Homeland Security, Nov 2010, Boston, United States. <emse-00552195>
  • Michel Agoyan, Jean-Max Dutertre, Amir-Pasha Mirbaha, David Naccache, Anne-Lise Ribotta, et al.. How to Flip a Bit?. On-Line Testing Symposium (IOLTS), 2010 IEEE 16th International, Jul 2010, Corfu, Greece. <10.1109/IOLTS.2010.5560194>. <emse-01130826>
  • Jean-Max Dutertre, Amir Pasha Mirbaha, Assia Tria, Bruno Robisson, Michel Agoyan. Revue expérimentale des techniques d'injection de fautes. Colloque nationale Groupement De Recherche SOC-SIP, Mar 2010, PARIS, France. <emse-00481623>
  • Jean-Max Dutertre, Assia Tria, Bruno Robisson. Injection de fautes par modification de l'horloge: application à l'AES.. Cryptopuce2009, Jun 2009, Porquerolle, France. <emse-00463505>
  • Jean-Max Dutertre, Assia Tria, Bruno Robisson, Michel Agoyan. Low cost fault injection method for security characterization. E-Smart 2009, Sep 2009, Sophia-Antipolis, France. <emse-00481620>
  • J.M. Dutertre, F.M. Roche, Guy Cathébras. Integration of Robustness in the Design of a Cell. SoC Design Methodologies - International Conference on Very Large Scale Integration of Systems-on-Chip, Montpellier, France, Kluwer Academic Publishers, pp.229-239, 2002. <lirmm-00268502>
  • Jean-Max Dutertre, Fernand-Michel Roche. Robustness of CMOS Circuits Designed for Space and Terrestrial Environment. XVI Conference on Design of Circuits and Integrated Systems, Nov 2001, Porto, Portugal. <emse-01130935>
  • Jean-Max Dutertre, Fernand-Michel Roche, Patrice Fouillat, Dean Lewis. Improving an SEU Hard Design using a Pulsed Laser. Radiation and Its Effects on Components and Systems, 2001. 6th European Conference on, Sep 2001, Grenoble, France. <10.1109/RADECS.2001.1159287>. <emse-01130950>

Poster2 documents

  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Giorgio Di Natale, et al.. Design of Bulk Built-In Current Sensors to Detect Single Event Effects and Laser-Induced Fault Injection Attempts . Joint MEDIAN–TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands. <emse-01099040>
  • Ingrid Exurville, Jacques Fournier, Jean-Max Dutertre, Bruno Robisson, Assia Tria. Practical measurements of data path delays for IP authentication & integrity verification. Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013 8th International Workshop on, Jul 2013, Darmstadt, Germany. <10.1109/ReCoSoC.2013.6581551>. <emse-01109140>

Article dans une revue10 documents

  • Nicolas Borrel, Clément Champeix, Edith Kussener, Wenceslas Rahajandraibe, Mathieu Lisart, et al.. Electrical model of an Inverter body biased structure in triple well technology under pulsed photoelectric laser stimulation. Microelectronics Reliability, Elsevier, 2015, <10.1016/j.microrel.2015.06.144>. <emse-01227386>
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS. Microelectronics Reliability, Elsevier, 2014, 54 (9-10), pp.2289-2294. <10.1016/j.microrel.2014.07.151>. <emse-01094805>
  • A. Sarafianos, C. Roscian, Jean-Max Dutertre, M. Lisart, A. Tria. Electrical modeling of the photoelectric effect induced by a pulsed laser applied to an SRAM cell. Microelectronics Reliability, Elsevier, 2013, 53 (9-11), pp.1300 - 1305. <10.1016/j.microrel.2013.07.125>. <emse-01100724>
  • Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, et al.. Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. Microelectronics Reliability, Elsevier, 2013, European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, 53 (9), pp.1320-1324. <10.1016/j.microrel.2013.07.069>. <emse-01100723>
  • Cyril Roscian, Florian Praden, Jean-Max Dutertre, Jacques Fournier, Assia Tria. Security characterisation of a hardened AES cryptosystem using a laser. "Technical Sciences", University of Warmia and Mazury publishing,, 2012. <emse-00742726>
  • A Sarafianos, R Llido, O Gagliano, V Serradeil, M Lisart, et al.. Building the electrical model of the Photoelectric Laser Stimulation of a PMOS transistor in 90nm technology. Microelectronics Reliability, Elsevier, 2012, pp.2035-2038. <10.1016/j.microrel.2012.06.047>. <emse-01110360>
  • Sarafianos Alexandre, R. Llido, Jean-Max Dutertre, Olivier Gagliano, Valérie Serradeil, et al.. Building the electricalmodel of the PhotoelectricLaserStimulation of a PMOS transistor in 90 nm technology. Microelectronics Reliability, Elsevier, 2012, 52, pp.2035-2038. <emse-00742622>
  • Jacques Jean-Alain Fournier, Michel Agoyan, Sylvain Bouquet, Jean-Max Dutertre, Jean-Baptiste Rigaud, et al.. Design and characterisation of an AES chip embedding countermeasures. International Journal of Intelligent Engineering Informatics, 2011, 1 (3/4), pp.328-347. <emse-00644114>
  • Michel Agoyan, Sylvain Bouquet, Jean-Max Dutertre, Jacques Jean-Alain Fournier, Jean-Baptiste Rigaud, et al.. Design and characterisation of an AES chip embedding countermeasures. International Journal of Intelligent Engineering Informatics, 2011, pp.00. <emse-00624400>
  • Michel Agoyan, Jean-Max Dutertre, David Naccache, Bruno Robisson, Assia Tria. When Clocks Fail: On Critical Paths and Clock Faults. Lecture notes in computer science, springer, 2010, Volume 6035/2010, pp.182-193. <10.1007/978-3-642-12510-2_13>. <emse-00505344>

Chapitre d'ouvrage2 documents

  • V. Beroulle, P. Candelier, S. De Castro, G. Di Natale, J.M. Dutertre, et al.. Laser-induced fault effects in security-dedicated circuits. VLSI-SoC: Internet of Things Foundations, elsevier, pp.220-240, 2015, 978-3-319-25278-0. <hal-01469495>
  • Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre, et al.. Laser-Induced Fault Effects in Security-Dedicated Circuits. VLSI-SoC: Internet of Things Foundations, 2015, 978-3-319-25278-0. <10.1007/978-3-319-25279-7_12>. <emse-01227387>

Autre publication1 document

  • Amine Debhaoui, Jean-Max Dutertre, Bruno Robisson, P. Orsatelli, Philippe Maurine, et al.. Injection of transient faults using electromagnetic pulses Practical results on a cryptographic system. Journal of Cryptology ePrint Archive: Report 2012/123. 2012. <emse-00742850>

Thèse1 document

  • Jean-Max Dutertre. Circuits Reconfigurables Robustes. Micro et nanotechnologies/Microélectronique. Université Montpellier II - Sciences et Techniques du Languedoc, 2002. Français. <tel-00010317>