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26 résultats
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triés par
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Architecture de Nœud basse Consommation et Intelligent pour des Réseaux de CapteurColloque sur les Objets et systèmes Connectés - COC'2021, IUT d'Aix-Marseille, Mar 2021, MARSEILLE, France
Communication dans un congrès
hal-03593064v1
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From multicore LDPC decoder implementations to FPGA decoder architectures: a case study2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec 2018, Bordeaux, France. pp.89-92
Communication dans un congrès
hal-02002993v1
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Sécurité Haut-débit pour les Systèmes Embarqués à base de FPGAsElectronique. Université de Bretagne Sud, 2011. Français. ⟨NNT : ⟩
Thèse
tel-00655959v2
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Distributed security for communications and memories in a multiprocessor architectureRAW 2011 (18th Reconfigurable Architectures Workshop), May 2011, Anchorage, Alaska, United States. pp.326-329, ⟨10.1109/IPDPS.2011.158⟩
Communication dans un congrès
ujm-00664284v1
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Ultra-Fast Downloading of Partial Bitstreams Through EthernetLecture Notes in Computer Science, 2009, vol. 5455., pp.72-83
Article dans une revue
hal-00488510v1
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High-throughput FFT architectures using HLS tools2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Oct 2022, Glasgow, United Kingdom. pp.1-4, ⟨10.1109/ICECS202256217.2022.9970886⟩
Communication dans un congrès
hal-04158201v1
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Lightweight reconfiguration security services for AXI-based MPSoCsFPL 2012 (22nd International Conference on Field Programmable Logic and Applications), Aug 2012, Oslo, Norway. pp.655-658, ⟨10.1109/FPL.2012.6339233⟩
Communication dans un congrès
hal-00750332v1
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Security FPGA AnalysisSecurity Trends for FPGAS
Chapitre d'ouvrage
istex
lirmm-00809327v1
From Secured to Secure Reconfigurable Systems, pp.7-46, 2011, ⟨10.1007/978-94-007-1338-3_2⟩ |
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Configurable Memory Security in Embedded SystemsACM Transactions on Embedded Computing Systems (TECS), 2013, 12/ (3), pp.71. ⟨10.1145/2442116.2442121⟩
Article dans une revue
hal-00670938v1
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Bus-based MPSoC security through communication protection: A latency-efficient alternativeFCCM 2012 (20th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines), Apr 2012, Toronto, Canada. pp.200-207
Communication dans un congrès
hal-00750343v1
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Lynq: A Lightweight Software Layer for Rapid SoC FPGA PrototypingColloque du GDR SOC2, Jun 2018, Paris, France
Communication dans un congrès
hal-01972754v1
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Architecture matérielle programmable optimisée pour les systèmes de communications numériquesConférence francophone d'informatique en Parallélisme, Architecture et Système, Jul 2021, Lyon, France
Communication dans un congrès
hal-03586312v1
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Architecture programmable pour les systèmes de communications numériquesGDR SoC2, Jun 2021, Rennes, France
Poster de conférence
hal-03586329v1
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Self-reconfigurable embedded systems: from modeling to implementationEngineering of Reconfigurable Systems and Algorithms, Jul 2010, Las Vegas, Nevada, United States
Communication dans un congrès
hal-00488577v1
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Conception d’architectures de FFT pour FPGA à base de modèles comportementauxConférence francophone d'informatique en Parallélisme, Architecture et Système (COMPAS 2022), Jul 2022, Amiens, France
Communication dans un congrès
hal-04158203v1
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Model-based Design of Efficient LDPC Decoder Architectures2018 IEEE 10th International Symposium on Turbo Codes & Iterative Information Processing (ISTC), Dec 2018, Hong Kong, China. pp.1-5
Communication dans un congrès
hal-02003001v1
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Efficient Key-Dependent Message Authentication in Reconfigurable HardwareInternational Conference on Field-Programmable Technology (FPT'11), Dec 2011, India
Communication dans un congrès
hal-00671191v1
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Lynq: A Lightweight Software Layer for Rapid SoC FPGA Prototyping28th International Conference on Field Programmable Logic and Applications (FPL 2018), 2018, Dublin, Ireland
Communication dans un congrès
hal-01972427v1
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Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems2008
Pré-publication, Document de travail
hal-00369078v1
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Model-Based Design of Flexible and Efficient LDPC Decoders on FPGA DevicesJournal of Signal Processing Systems, 2020, ⟨10.1007/s11265-020-01519-0⟩
Article dans une revue
hal-02490238v1
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A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU DevicesIEEE Embedded Systems Letters, 2014, 6 (2), pp.29-32. ⟨10.1109/LES.2014.2311317⟩
Article dans une revue
hal-01002957v1
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Generation of efficient self-adaptive hardware polar decoders using high-level synthesisIEEE International Workshop on Signal Processing Systems (SIPS), Oct 2019, Nanjing, China
Communication dans un congrès
hal-02490245v1
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Model-based Design of Hardware SC Polar Decoders for FPGAsACM Transactions on Reconfigurable Technology and Systems (TRETS), 2020, 13 (2)
Article dans une revue
hal-02612069v1
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Fast Design of Reliable, Flexible and High-Speed AWGN architectures with High Level Synthesis2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec 2018, Bordeaux, France. pp.661-664
Communication dans un congrès
hal-02002990v1
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End-to-End Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable SystemsGuy Gogniat, Dragomir Milojevic, Adam Morawiec, Ahmet Erdogan. Algorithm-Architecture Matching for Signal and Image Processing, Springer, pp.171-194, 2011, Lecture Notes in Electrical Engineering
Chapitre d'ouvrage
hal-00670954v1
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SecURe DPR: Secure update preventing replay attacks for dynamic partial reconfigurationFPL: Field Programmable Logic, Aug 2012, Oslo, Norway. pp.57-62, ⟨10.1109/FPL.2012.6339241⟩
Communication dans un congrès
lirmm-00818735v1
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