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56 résultats
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triés par
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Impact of contact and channel resistance on the frequency-dependent capacitance and conductance of pseudo-MOSFETSolid-State Electronics, 2019, 159, pp.197-203. ⟨10.1016/j.sse.2019.03.059⟩
Article dans une revue
hal-02321909v1
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Electrical characterization of ultra-thin silicon-on-insulator substrates : static and split C–V measurements in the Pseudo–MOSFET configuration4th Int. Conference on Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film Technology (ULSIC ), Jul 2013, Villard de Lans, France. pp.203-208
Communication dans un congrès
hal-01182173v1
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Parasitic bipolar effect in advanced FD SOI MOSFETs: experimental evidence and gain extraction10th EUROSOI Workshop, Jan 2014, Tarrogona, Spain
Communication dans un congrès
hal-02008226v1
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Second harmonic generation for contactless non-destructive characterization of silicon on insulator wafersSolid-State Electronics, 2016, 115, pp.237 - 243. ⟨10.1016/j.sse.2015.08.006⟩
Article dans une revue
hal-01893414v1
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Impact of Blend Morphology on Interface State Recombination in Bulk Heterojunction Organic Solar CellsAdvanced Functional Materials, 2015, pp.10.1002/adfm.201401633. ⟨10.1002/adfm.201401633⟩
Article dans une revue
hal-01100102v1
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Interface trap density evaluation on bare silicon-on-insulator wafers using the quasi-static capacitance techniqueJournal of Applied Physics, 2016, 119 (17), pp.175702. ⟨10.1063/1.4947498⟩
Article dans une revue
hal-01947679v1
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Transient second harmonic generation and correlation with Ψ-MOSFET in SOI wafers2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Jan 2016, Vienna, Austria. pp.222-225, ⟨10.1109/ULIS.2016.7440093⟩
Communication dans un congrès
hal-01974394v1
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Low-frequency noise in bare SOI wafers: Experiments and model2015 ESSDERC - 45th European Solid-State Device Research Conference, Sep 2015, Graz, Austria. pp.286-289, ⟨10.1109/ESSDERC.2015.7324770⟩
Communication dans un congrès
hal-02004194v1
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Effet de champ et blocage de Coulomb dans des nanostructures de silicium élaborées par microscopie à force atomiquePhysique [physics]. Institut National Polytechnique de Grenoble - INPG, 2005. Français. ⟨NNT : ⟩
Thèse
tel-00097465v1
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Second harmonic generation for non-destructive characterization of silicon-on-insulator substrates2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Jan 2015, Bologna, Italy. pp.185-188, ⟨10.1109/ULIS.2015.7063744⟩
Communication dans un congrès
hal-02004048v1
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Potential of nanonets for the 3D integration of biosensors on CMOS (invited)Journées Nationales Nanofils Semiconducteurs Journées Nationales Nanofils Semiconducteurs, Lyon, 13-15 Nov. 2019, Nov 2019, Lyon, France
Communication dans un congrès
hal-02400730v1
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Split-CV for pseudo-MOSFET characterization: Experimental setups and associated parameter extraction methods2014 International Conference on Microelectronic Test Structures (ICMTS), Mar 2014, Udine, Italy. pp.14-19, ⟨10.1109/ICMTS.2014.6841461⟩
Communication dans un congrès
hal-02003797v1
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(Invited) Non-Destructive Characterization of Dielectric - Semiconductor Interfaces by Second Harmonic Generation229th ECS Meetings: 7th Int. Symposium on Dielectrics for Nanosystems: Materials Science, Processing, Reliability and Manufaturing - and - Solid State Topics General Session, D. Misra, K. Sundaram, H. Iwai, T. Chikyo, Y. Obeng, Z. Chen, D. Bauza, O. Leonte and K. Shimanura, May 2016, San Diego, United States
Communication dans un congrès
hal-02007827v1
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Layer thickness impact on Second Harmonic Generation characterization of SOI wafers2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2017, Athens, Greece. pp.184-187, ⟨10.1109/ULIS.2017.7962557⟩
Communication dans un congrès
hal-01974416v1
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Optical Switching of Porphyrin-Coated Silicon Nanowire Field Effect TransistorsNano Letters, 2007, 7 (6), pp.1454-1458. ⟨10.1021/nl0630485⟩
Article dans une revue
hal-00700064v1
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Characterization of Silicon-On-Insulator films with pseudo metal-oxide-semiconductor field-effect transistor: correlation between contact pressure, crater morphology and series resistance.Applied Physics Letters, 2008, XX (XX, XX183511), pp.1-3
Article dans une revue
hal-00391712v1
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Electrical detection of bacteria on SOI film using the pseudo-MOSFET configurationInternational Workshop on Semi-conducting Nanomaterials for Health, Environment and Security Applications, Nanonets2Sense, Nov 2018, Grenoble, France
Communication dans un congrès
hal-02016817v1
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Effect of back gate on parasitic bipolar effect in FD SOI MOSFETs2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2014, Millbrae, United States. pp.5.8, ⟨10.1109/S3S.2014.7028210⟩
Communication dans un congrès
hal-02003967v1
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Scanning microwave microscopy for non-destructive characterization of SOI wafers2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Jan 2016, Vienna, Austria. pp.238-241, ⟨10.1109/ULIS.2016.7440097⟩
Communication dans un congrès
hal-02004364v1
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Back-gated InGaAs-on-insulator lateral N+NN+ MOSFET: Fabrication and typical conduction mechanismsSolid-State Electronics, 2017, 128, pp.80-86. ⟨10.1016/j.sse.2016.10.019⟩
Article dans une revue
hal-02003226v1
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Special characterization techniques for advanced FDSOI process2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2015, Rohnert Park, United States. pp.9a.1, ⟨10.1109/S3S.2015.7333543⟩
Communication dans un congrès
hal-02004273v1
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Second Harmonic Generation: A Non-Destructive Characterization Method for Dielectric-Semiconductor Interfaces2018 International Semiconductor Conference (CAS), Oct 2018, Sinaia, Romania. pp.35-42, ⟨10.1109/SMICND.2018.8539758⟩
Communication dans un congrès
hal-01974421v1
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Out-of-equilibrium body potential measurements in pseudo-MOSFET for biosensing2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2017, Athens, Greece. pp.19-22, ⟨10.1109/ULIS.2017.7962590⟩
Communication dans un congrès
hal-02007128v1
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Out-of-Equilibrium Body Potential Measurements in Pseudo-MOSFET for Sensing ApplicationsSolid-State Electronics, 2018, 143, pp.69-76. ⟨10.1016/j.sse.2017.11.010⟩
Article dans une revue
hal-01685404v1
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Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET ConfigurationIEEE Transactions on Electron Devices, 2015, 62 (9), pp.2717-2723. ⟨10.1109/TED.2015.2454438⟩
Article dans une revue
hal-01947654v1
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Back-gate effects and detailed characterization of junctionless transistor2015 ESSDERC - 45th European Solid-State Device Research Conference, Sep 2015, Graz, Austria. pp.282-285, ⟨10.1109/ESSDERC.2015.7324769⟩
Communication dans un congrès
hal-02004181v1
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A simple compact model for carrier distribution and its application in single-, double- and triple-gate junctionless transistors2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Jan 2015, Bologna, Italy. pp.277-280, ⟨10.1109/ULIS.2015.7063827⟩
Communication dans un congrès
hal-02004057v1
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Selected SOI puzzles and tentative answers1st Ukrainian-French Symposium 'Semiconductor-On-Insulator Materials, Devices and Circuits: Physics, Technology and Diagnostics, Oct 2010, Kiev, Ukraine
Communication dans un congrès
hal-00604923v1
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Characterization of heavily doped SOI wafers under pseudo-MOSFET configurationSolid-State Electronics, 2013, 90, pp.65-72. ⟨10.1016/j.sse.2013.02.050⟩
Article dans une revue
istex
hal-01001965v1
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Experimental and simulation investigation of the out-of-equilibrium phenomena on the pseudo-MOSFET configuration under transient linear voltage rampsSolid-State Electronics, 2020, 168, pp.107721. ⟨10.1016/j.sse.2019.107721⟩
Article dans une revue
hal-03171017v1
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