Nombre de documents

5

CV de Imran Wali


Communication dans un congrès4 documents

  • Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard. An Experimental Comparative Study of Fault-Tolerant Architectures. VALID: Advances in System Testing and Validation Lifecycle, Nov 2015, Barcelone, Spain. IARIA XPS Press, 7th International Conference on Advances in System Testing and Validation Lifecycle, pp.1-6, 2015, <http://www.iaria.org/conferences2015/VALID15.html>. <lirmm-01354754>
  • Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard. An effective hybrid fault-tolerant architecture for pipelined cores. ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. Test Symposium (ETS), 2015 20th IEEE European, pp.1-6, 2015, <10.1109/ETS.2015.7138733>. <lirmm-01272730>
  • Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda. Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. IOLTS: International On-Line Testing Symposium, Jul 2015, Halkidiki, Greece. On-Line Testing Symposium (IOLTS), 2015 IEEE 21st International, pp.89-94, 2015, <http://tima.imag.fr/conferences/iolts/iolts15/>. <10.1109/IOLTS.2015.7229838>. <lirmm-01272735>
  • Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, et al.. Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2014, Warsaw, Poland. Design and Diagnostics of Electronic Circuits Systems, 17th International Symposium on, pp.223-225, 2014, <10.1109/DDECS.2014.6868794>. <lirmm-01248598>

Article dans une revue1 document

  • Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, et al.. A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. Journal of Electronic Testing, Springer Verlag, 2016, 32 (2), pp.147-161. <10.1007/s10836-016-5578-0>. <lirmm-01354746>