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	Pour les 22 documents Envoyer sur ORCID RSS ATOM Exporter BibTeX XML-TEI CSV RTF EndNote PDF HTML Export avancé	Page :	triés par Pertinence Auteur A→Z Auteur Z→A Titre A→Z Titre Z→A Date de publication croissante Date de publication décroissante Date de dépôt croissante Date de dépôt décroissante

		Efficient Tree Topology for FPGA Interconnect Network Zied Marrakchi , Hayder Mrabet , Emna Amouri , Habib Mehrez GLSVLSI ACM Great Lakes Symposium on VLSI, May 2008, Orlando, Florida, United States. pp.321-326, ⟨10.1145/1366110.1366186⟩ Communication dans un congrès hal-01301523v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Performances comparison between Multilevel hierarchical and Mesh FPGA Zied Marrakchi , Hayder Mrabet , Habib Mehrez DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Sep 2006, Tunis, Tunisia. pp.166-171, ⟨10.1109/DTIS.2006.1708712⟩ Communication dans un congrès hal-01338430v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure Hayder Mrabet , Zied Marrakchi , Pierre Souillot , Habib Mehrez , André Tissot ReCoSoC 2006 - 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Jul 2006, Montpellier, France. pp.117--123 Communication dans un congrès hal-01372838v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Automatic Layout Generator of Domain Specific FPGA: Hayder Mrabet , Husain Parvez , Zied Marrakchi , Habib Mehrez ICM International Conference on Microelectronics, Dec 2008, Sharjah, United Arab Emirates. pp.183-186, ⟨10.1109/ICM.2008.5393493⟩ Communication dans un congrès hal-01299216v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		The Effect of LUT and Cluster Size on a Tree based FPGA Architecture Umer Farooq , Zied Marrakchi , Hayder Mrabet , Habib Mehrez ReConFig International Conference on Reconfigurable Computing and FPGAs, Dec 2008, Cancun, Mexico. pp.115-120, ⟨10.1109/ReConFig.2008.28⟩ Communication dans un congrès hal-01299218v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Performances Comparison between Multilevel Hierarchical and Mesh FPGA Interconnects Zied Marrakchi , Hayder Mrabet , Christian Masson , Habib Mehrez International Journal of Electronics, 2008, 95 (3), pp.275-289. ⟨10.1080/00207210701828069⟩ Article dans une revue hal-01195976v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		FPGA Interconnect Topologies Exploration Zied Marrakchi , Hayder Mrabet , Habib Mehrez International Journal of Reconfigurable Computing, 2009, 2009, pp.259837. ⟨10.1155/2009/259837⟩ Article dans une revue hal-01197287v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances Zied Marrakchi , Hayder Mrabet , Christian Masson , Habib Mehrez NoC ACM/IEEE International Symposium on Networks-on-Chip, May 2007, Princeton, United States. pp.243-252, ⟨10.1109/NOCS.2007.27⟩ Communication dans un congrès hal-01305788v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Automatic Layout of Scalable Embedded Field Programmable Gate Array Hayder Mrabet , Zied Marrakchi , Habib Mehrez , André Tissot ICEEC 2004 - International Conference on Electrical Electronic and Computer Engineering, Sep 2004, Cairo, Egypt. pp.469-472, ⟨10.1109/ICEEC.2004.1374502⟩ Communication dans un congrès hal-01521128v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Configuration tools for a new multilevel hierarchical FPGA Zied Marrakchi , Hayder Mrabet , Habib Mehrez FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2006, Monterey, California, United States. pp.229-229, ⟨10.1145/1117201.1117248⟩ Communication dans un congrès hal-01338217v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Evaluation of Hierarchical FPGA partitioning methodologies based on architecture Rent Parameter Zied Marrakchi , Hayder Mrabet , Habib Mehrez PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Jun 2006, Otranto, Italy. pp.85-88, ⟨10.1109/RME.2006.1689902⟩ Communication dans un congrès hal-01338243v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Generic Techniques and CAD tools for automated generation of FPGA Layout Husain Parvez , Hayder Mrabet , Habib Mehrez PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Jun 2008, Istanbul, Turkey. pp.141-144, ⟨10.1109/RME.2008.4595745⟩ Communication dans un congrès hal-01301526v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Implementation of Scalable Embedded FPGA for SOC Hayder Mrabet , Zied Marrakchi , Habib Mehrez , André Tissot ReCoSoC 2005 - 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Jun 2005, Montpellier, France. pp.74-77 Communication dans un congrès hal-01419656v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		A new Multilevel Hierarchical MFPGA and its suitable configuration tools Zied Marrakchi , Hayder Mrabet , Habib Mehrez ISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, Mar 2006, Karlsruhe, Germany. pp.263-268, ⟨10.1109/ISVLSI.2006.6⟩ Communication dans un congrès hal-01338233v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Implementation of Scalable Embedded FPGA for SOC Hayder Mrabet , Zied Marrakchi , Habib Mehrez , André Tissot DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Sep 2006, Tunis, Tunisia. pp.74-77, ⟨10.1109/DTIS.2006.1708687⟩ Communication dans un congrès hal-01338253v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Efficient Mesh of Tree Interconnect for FPGA Architecture Zied Marrakchi , Hayder Mrabet , Christian Masson , Habib Mehrez ICFPT International Conference on Field-Programmable Technology, Dec 2007, Kitakyushu, Japan. pp.269-272, ⟨10.1109/FPT.2007.4439263⟩ Communication dans un congrès hal-01305972v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Hierarchical FPGA clustering to improve routability Zied Marrakchi , Hayder Mrabet , Habib Mehrez PRIME 2005 - IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Jul 2005, Lausanne, Switzerland. pp.165-168, ⟨10.1109/RME.2005.1543029⟩ Communication dans un congrès hal-01419664v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		A Routability Driven Partitioning and Detailed Placement Approach for Multilevel Hierarchical FPGA Zied Marrakchi , Hayder Mrabet , Grégory Souffleteau , Christian Masson , Habib Mehrez FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2007, Monterey, Californie, United States. pp.225-225 Communication dans un congrès hal-01311525v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation Zied Marrakchi , Hayder Mrabet , Habib Mehrez ReConFig 2005 - International Conference on Reconfigurable Computing and FPGAs, Sep 2005, Puebla City, Mexico. pp.21-25, ⟨10.1109/RECONFIG.2005.23⟩ Communication dans un congrès hal-01372839v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Design and Optimization of Reconfigurable Architectures: The FPGA Family Hayder Mrabet Micro and nanotechnologies/Microelectronics. Université Pierre et Marie Curie Paris VI, 2009. English. ⟨NNT : ⟩ Thèse tel-03321687v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		Performances Improvement of FPGA using Novel Multilevel Hierarchical Interconnection Structure Hayder Mrabet , Zied Marrakchi , Pierre Souillot , Habib Mehrez ICCAD IEEE/ACM International Conference on Computer-Aided Design, Nov 2006, San Jose, California, United States. pp.675-679, ⟨10.1109/ICCAD.2006.320012⟩ Communication dans un congrès hal-01338460v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More
		A multilevel hierarchical interconnection structure for FPGA Hayder Mrabet , Zied Marrakchi , Pierre Souillot , Habib Mehrez FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2006, Monterey, California, United States. pp.225-225, ⟨10.1145/1117201.1117239⟩ Communication dans un congrès hal-01338215v1	Envoyer sur ORCID Exporter BibTeX XML-TEI Dublin Core DC Terms EndNote DataCite Export avancé Partager Gmail Facebook X LinkedIn More

Efficient Tree Topology for FPGA Interconnect Network

Zied Marrakchi , Hayder Mrabet , Emna Amouri , Habib Mehrez

GLSVLSI ACM Great Lakes Symposium on VLSI, May 2008, Orlando, Florida, United States. pp.321-326, ⟨10.1145/1366110.1366186⟩

Communication dans un congrès hal-01301523v1

Performances comparison between Multilevel hierarchical and Mesh FPGA

Zied Marrakchi , Hayder Mrabet , Habib Mehrez

DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Sep 2006, Tunis, Tunisia. pp.166-171, ⟨10.1109/DTIS.2006.1708712⟩

Communication dans un congrès hal-01338430v1

Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure

Hayder Mrabet , Zied Marrakchi , Pierre Souillot , Habib Mehrez , André Tissot

ReCoSoC 2006 - 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Jul 2006, Montpellier, France. pp.117--123

Communication dans un congrès hal-01372838v1

Automatic Layout Generator of Domain Specific FPGA:

Hayder Mrabet , Husain Parvez , Zied Marrakchi , Habib Mehrez

ICM International Conference on Microelectronics, Dec 2008, Sharjah, United Arab Emirates. pp.183-186, ⟨10.1109/ICM.2008.5393493⟩

Communication dans un congrès hal-01299216v1

The Effect of LUT and Cluster Size on a Tree based FPGA Architecture

Umer Farooq , Zied Marrakchi , Hayder Mrabet , Habib Mehrez

ReConFig International Conference on Reconfigurable Computing and FPGAs, Dec 2008, Cancun, Mexico. pp.115-120, ⟨10.1109/ReConFig.2008.28⟩

Communication dans un congrès hal-01299218v1

Performances Comparison between Multilevel Hierarchical and Mesh FPGA Interconnects

Zied Marrakchi , Hayder Mrabet , Christian Masson , Habib Mehrez

International Journal of Electronics, 2008, 95 (3), pp.275-289. ⟨10.1080/00207210701828069⟩

Article dans une revue hal-01195976v1

FPGA Interconnect Topologies Exploration

Zied Marrakchi , Hayder Mrabet , Habib Mehrez

International Journal of Reconfigurable Computing, 2009, 2009, pp.259837. ⟨10.1155/2009/259837⟩

Article dans une revue hal-01197287v1

Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances

Zied Marrakchi , Hayder Mrabet , Christian Masson , Habib Mehrez

NoC ACM/IEEE International Symposium on Networks-on-Chip, May 2007, Princeton, United States. pp.243-252, ⟨10.1109/NOCS.2007.27⟩

Communication dans un congrès hal-01305788v1

Automatic Layout of Scalable Embedded Field Programmable Gate Array

Hayder Mrabet , Zied Marrakchi , Habib Mehrez , André Tissot

ICEEC 2004 - International Conference on Electrical Electronic and Computer Engineering, Sep 2004, Cairo, Egypt. pp.469-472, ⟨10.1109/ICEEC.2004.1374502⟩

Communication dans un congrès hal-01521128v1

Configuration tools for a new multilevel hierarchical FPGA

Zied Marrakchi , Hayder Mrabet , Habib Mehrez

FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2006, Monterey, California, United States. pp.229-229, ⟨10.1145/1117201.1117248⟩

Communication dans un congrès hal-01338217v1

Evaluation of Hierarchical FPGA partitioning methodologies based on architecture Rent Parameter

Zied Marrakchi , Hayder Mrabet , Habib Mehrez

PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Jun 2006, Otranto, Italy. pp.85-88, ⟨10.1109/RME.2006.1689902⟩

Communication dans un congrès hal-01338243v1

Generic Techniques and CAD tools for automated generation of FPGA Layout

Husain Parvez , Hayder Mrabet , Habib Mehrez

PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Jun 2008, Istanbul, Turkey. pp.141-144, ⟨10.1109/RME.2008.4595745⟩

Communication dans un congrès hal-01301526v1

Implementation of Scalable Embedded FPGA for SOC

Hayder Mrabet , Zied Marrakchi , Habib Mehrez , André Tissot

ReCoSoC 2005 - 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Jun 2005, Montpellier, France. pp.74-77

Communication dans un congrès hal-01419656v1

A new Multilevel Hierarchical MFPGA and its suitable configuration tools

Zied Marrakchi , Hayder Mrabet , Habib Mehrez

ISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, Mar 2006, Karlsruhe, Germany. pp.263-268, ⟨10.1109/ISVLSI.2006.6⟩

Communication dans un congrès hal-01338233v1

Implementation of Scalable Embedded FPGA for SOC

Hayder Mrabet , Zied Marrakchi , Habib Mehrez , André Tissot

DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Sep 2006, Tunis, Tunisia. pp.74-77, ⟨10.1109/DTIS.2006.1708687⟩

Communication dans un congrès hal-01338253v1

Efficient Mesh of Tree Interconnect for FPGA Architecture

Zied Marrakchi , Hayder Mrabet , Christian Masson , Habib Mehrez

ICFPT International Conference on Field-Programmable Technology, Dec 2007, Kitakyushu, Japan. pp.269-272, ⟨10.1109/FPT.2007.4439263⟩

Communication dans un congrès hal-01305972v1

Hierarchical FPGA clustering to improve routability

Zied Marrakchi , Hayder Mrabet , Habib Mehrez

PRIME 2005 - IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Jul 2005, Lausanne, Switzerland. pp.165-168, ⟨10.1109/RME.2005.1543029⟩

Communication dans un congrès hal-01419664v1

A Routability Driven Partitioning and Detailed Placement Approach for Multilevel Hierarchical FPGA

Zied Marrakchi , Hayder Mrabet , Grégory Souffleteau , Christian Masson , Habib Mehrez

FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2007, Monterey, Californie, United States. pp.225-225

Communication dans un congrès hal-01311525v1

Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation

Zied Marrakchi , Hayder Mrabet , Habib Mehrez

ReConFig 2005 - International Conference on Reconfigurable Computing and FPGAs, Sep 2005, Puebla City, Mexico. pp.21-25, ⟨10.1109/RECONFIG.2005.23⟩

Communication dans un congrès hal-01372839v1

Design and Optimization of Reconfigurable Architectures: The FPGA Family

Hayder Mrabet

Micro and nanotechnologies/Microelectronics. Université Pierre et Marie Curie Paris VI, 2009. English. ⟨NNT : ⟩

Thèse tel-03321687v1

Performances Improvement of FPGA using Novel Multilevel Hierarchical Interconnection Structure

Hayder Mrabet , Zied Marrakchi , Pierre Souillot , Habib Mehrez

ICCAD IEEE/ACM International Conference on Computer-Aided Design, Nov 2006, San Jose, California, United States. pp.675-679, ⟨10.1109/ICCAD.2006.320012⟩

Communication dans un congrès hal-01338460v1

A multilevel hierarchical interconnection structure for FPGA

Hayder Mrabet , Zied Marrakchi , Pierre Souillot , Habib Mehrez

FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2006, Monterey, California, United States. pp.225-225, ⟨10.1145/1117201.1117239⟩

Communication dans un congrès hal-01338215v1

Filtrer vos résultats

Efficient Tree Topology for FPGA Interconnect Network

Performances comparison between Multilevel hierarchical and Mesh FPGA

Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure

Automatic Layout Generator of Domain Specific FPGA:

The Effect of LUT and Cluster Size on a Tree based FPGA Architecture

Performances Comparison between Multilevel Hierarchical and Mesh FPGA Interconnects

FPGA Interconnect Topologies Exploration

Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances

Automatic Layout of Scalable Embedded Field Programmable Gate Array

Configuration tools for a new multilevel hierarchical FPGA

Evaluation of Hierarchical FPGA partitioning methodologies based on architecture Rent Parameter

Generic Techniques and CAD tools for automated generation of FPGA Layout

Implementation of Scalable Embedded FPGA for SOC

A new Multilevel Hierarchical MFPGA and its suitable configuration tools

Implementation of Scalable Embedded FPGA for SOC

Efficient Mesh of Tree Interconnect for FPGA Architecture

Hierarchical FPGA clustering to improve routability

A Routability Driven Partitioning and Detailed Placement Approach for Multilevel Hierarchical FPGA

Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation

Design and Optimization of Reconfigurable Architectures: The FPGA Family

Performances Improvement of FPGA using Novel Multilevel Hierarchical Interconnection Structure

A multilevel hierarchical interconnection structure for FPGA