CV de Habib Mehrez

Umer Farooq, Habib Mehrez, Muhammad Khurram Bhatti. Inter-FPGA interconnect topologies exploration for multi-FPGA systems. Design Automation for Embedded Systems, Springer Verlag, 2018, 22 (1-2), pp.117 - 140. ⟨10.1007/s10617-018-9207-2⟩. ⟨hal-01833307⟩

Roselyne Chotin-Avot, Umer Farooq, Muhammad Moazam Azeem, Maminionja Ravoson, Habib Mehrez. Novel architectural space exploration environment for multi-FPGA based prototyping systems. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2018, 56, pp.169 - 183. ⟨10.1016/j.micpro.2017.12.006⟩. ⟨hal-01667303⟩

Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations. Journal of Signal Processing Systems, Springer, 2016, pp.1-12. ⟨10.1007/s11265-016-1104-y⟩. ⟨hal-01259067⟩

Sonda Chtourou, Zied Marrakchi, Emna Amouri, Vinod Pangracious, Mohamed Abid, et al.. Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2016, 40, pp.16-26. ⟨10.1016/j.micpro.2015.11.011⟩. ⟨hal-01369085⟩

Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid. Signal multiplexing approach to improve inter-FPGA bandwidth of prototyping platform. Design Automation for Embedded Systems, Springer Verlag, 2015, 19 (3), pp.223--242. ⟨10.1007/s10617-014-9155-4⟩. ⟨hal-01369151⟩

Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. Authenticated Encryption on FPGAs from the Static Part to the Reconfigurable Part. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2014, 38 (6), pp.526-538. ⟨10.1016/j.micpro.2014.03.006⟩. ⟨hal-01017913⟩

Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. Low cost Solutions for Secure Remote Reconfiguration of FPGAs. International Journal of Embedded Systems, Inderscience, 2014, 6 (2-3), pp.257-265. ⟨10.1504/ijes.2014.063824⟩. ⟨hal-01017873⟩

Vinod Pangracious, Emna Amouri, Zied Marrakchi, Habib Mehrez. Architecture level optimization of 3-dimensional tree-based FPGA. Microelectronics Journal, Elsevier, 2014, 45 (4), pp.355-366. ⟨10.1016/j.mejo.2013.12.011⟩. ⟨hal-00944759⟩

Nidhameddine Belhadj, Zied Marrakchi, Mohamed Ali Ben Ayed, Nouri Masmoudi, Habib Mehrez. MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder. International Journal of Embedded and Real-Time Communication Systems, IGI Global, 2014, 5 (2), pp.43--60. ⟨10.4018/ijertcs.2014040104⟩. ⟨hal-01372865⟩

Emna Amouri, Habib Mehrez, Zied Marrakchi. Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA. International Journal of Reconfigurable Computing, Hindawi Publishing Corporation, 2013, 2013 (802436), pp.24. ⟨10.1155/2013/802436⟩. ⟨hal-01195951⟩

Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid. Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform. International Journal of Reconfigurable Computing, Hindawi Publishing Corporation, 2013, 2013, pp.853510. ⟨10.1155/2013/853510⟩. ⟨hal-01195952⟩

Arwa Ben Dhia, S. N. Pagliarini, Lirida Naviner, Habib Mehrez, Philippe Matherat. A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs. Microelectronics Reliability, Elsevier, 2013, 53 (9-11), pp.1189-1193. ⟨10.1016/j.microrel.2013.06.014⟩. ⟨hal-01195954⟩

Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez. Exploring redundant arithmetics in computer-aided design of arithmetic datapaths. Integration, the VLSI Journal, Elsevier, 2013, 46 (2), pp.104-118. ⟨10.1016/j.vlsi.2012.02.002⟩. ⟨hal-01197289⟩

Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez. A New Heterogeneous Tree-based Application Specific FPGA and Its Comparison with Mesh-based Application Specific FPGA. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2012, 36 (8), pp.588-605. ⟨10.1016/j.micpro.2012.06.012⟩. ⟨hal-01197292⟩

Husain Parvez, Zied Marrakchi, Alp Kilic, Habib Mehrez. Application-Specific FPGA using heterogeneous logic blocks. ACM Transactions on Reconfigurable Technology and Systems (TRETS), ACM, 2011, 4 (3), pp.1-24. ⟨10.1145/2000832.2000836⟩. ⟨hal-01197270⟩

Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi. Exploration of Heterogeneous FPGA Arcrchitectures. International Journal of Reconfigurable Computing, Hindawi Publishing Corporation, 2011, 2011, pp.121404. ⟨10.1155/2011/121404⟩. ⟨hal-01197276⟩

Zied Guitouni, Roselyne Chotin-Avot, Mohsen Machhout, Habib Mehrez, Rached Tourki. High Performances ASIC Based Elliptic Curve Cryptographic Processor over GF(2m). International Journal of Computer Applications, Foundation of Computer Science, 2011, Special Issue on Network Security and Cryptography (NSC) (4), pp.1-10. ⟨10.5120/4342-039⟩. ⟨hal-01197278⟩

Zied Marrakchi, Hayder Mrabet, Habib Mehrez. FPGA Interconnect Topologies Exploration. International Journal of Reconfigurable Computing, Hindawi Publishing Corporation, 2009, 2009, pp.259837. ⟨10.1155/2009/259837⟩. ⟨hal-01197287⟩

Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez. Performances Comparison between Multilevel Hierarchical and Mesh FPGA Interconnects. International Journal of Electronics, Taylor & Francis, 2008, 95 (3), pp.275-289. ⟨10.1080/00207210701828069⟩. ⟨hal-01195976⟩

Roselyne Chotin-Avot, Habib Mehrez. Hardware implementation of discrete stochastic arithmetic. Numerical Algorithms, Springer Verlag, 2004, 37 (1-4), pp.21-33. ⟨10.1023/B:NUMA.0000049455.07441.ee⟩. ⟨hal-01195967⟩

Hassan Aboushady, Yannick Dumonteix, Marie-Minerve Louërat, Habib Mehrez. Efficient Polyphase decomposition of Comb decimation filters in sigma-delta analog-to-digital converters. IEEE Transactions on Circuits and Systems Part 2 Analog and Digital Signal Processing, Institute of Electrical and Electronics Engineers (IEEE), 2001, 48 (10), pp.898-903. ⟨10.1109/82.974776⟩. ⟨hal-01197317⟩

Mourad Aberbour, Alain Houelle, Habib Mehrez, Nicolas Vaucher, Alain Guyot. On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 1998, 6 (1), pp.114-121. ⟨10.1109/92.661253⟩. ⟨hal-00014712⟩

Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. AEGIS-Based Efficient Solution for Secure Reconfiguration of FPGAs. Cryptography and Security in Computing Systems, Jan 2016, Prague, Czech Republic. pp.37-40, ⟨10.1145/2858930.2858937⟩. ⟨hal-01259069⟩

Muhammad Moazam Azeem, Roselyne Chotin-Avot, Umer Farooq, Maminionja Ravoson, Habib Mehrez. Multiple FPGAs based prototyping and debugging with complete design flow. IDT 2016 - 11th International Design & Test Symposium, Dec 2016, Hammamet, Tunisia. pp.171-176, ⟨10.1109/IDT.2016.7843035⟩. ⟨hal-01657908⟩

Qingshan Tang, Matthieu Tuna, Habib Mehrez. Multi-FPGA Prototyping Board Issue : the FPGA I/O Bottleneck. International Conference on Embedded Computer Systems : Architectures, Modeling, and Simulation, Jul 2014, Agios Konstantinos, Greece. pp.207-214, ⟨10.1109/SAMOS.2014.6893213⟩. ⟨hal-01073937⟩

Qingshan Tang, Matthieu Tuna, Habib Mehrez. Performance Comparison between Multi-FPGA Prototyping Platforms: Hardwired Off-the-Shelf, Cabling and Custom. International Symposium on Field-Programmable Custom Computing Machines, May 2014, Boston, MA, United States. pp.125-132, ⟨10.1109/FCCM.2014.44⟩. ⟨hal-01073939⟩

Qingshan Tang, Matthieu Tuna, Habib Mehrez. Future Inter-FPGA Communication Architecture for Multi-FPGA Based Prototyping. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Feb 2014, Monterey, CA, United States. pp.251-251, ⟨10.1145/2554688.2554747⟩. ⟨hal-00969240⟩

Jung Kyu Chae, Paul Mougeat, Jean-Arnaud François, Roselyne Chotin-Avot, Habib Mehrez. A reference-based specification tool for creating reliable library development specifications. 12th International New Circuits and Systems Conference, NEWCAS 2014, Jun 2014, Trois-Rivieres, QC, Canada. pp.133-136, ⟨10.1109/NEWCAS.2014.6934001⟩. ⟨hal-01217236⟩

Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. FPGA-Based High Performance AES-GCM Using Efficient Karatsuba Ofman Algorithm. 10th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications, ARC 2014, Apr 2014, Vilamoura, Portugal. pp.13-24, ⟨10.1007/978-3-319-05960-0_2⟩. ⟨hal-01219833⟩

Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri. Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy. FPL 2014 - 24th International Conference on Field Programmable Logic and Applications, Sep 2014, Munich, Germany. pp.1-4, ⟨10.1109/FPL.2014.6927389⟩. ⟨hal-01162011⟩

Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri. Impact of defect tolerance techniques on the criticality of a SRAM-based Mesh of Cluster FPGA. ReConFig 2014 - International Conference on ReConFigurable Computing and FPGAs, Dec 2014, Cancun, Mexico. pp.1-6, ⟨10.1109/ReConFig.2014.7032508⟩. ⟨hal-01162066⟩

Boukary Ouattara, Lise Doyen, David Ney, Habib Mehrez, Pirouz Bazargan-Sabet, et al.. Redundancy Method to assess Electromigration Lifetime in power grid design. IEEE International Interconnect Technology Conference (IITC),, Jun 2013, Kyoto, Japan. pp.81-83, ⟨10.1109/IITC.2013.6615570⟩. ⟨hal-00915971⟩

Vinod Pangracious, Habib Mehrez, Umer Farooq, Zied Marrakchi. High Performance 3-Dimensional Heterogeneous Tree-based FPGA Architectures (HT-FPGA). FPGAworld'13 - The 10th FPGAworld Conference, Sep 2013, Stockholm, Sweden. pp.3:1-3:6, ⟨10.1145/2513683.2513686⟩. ⟨hal-00873151⟩

Vinod Pangracious, Emna Amouri, Habib Mehrez, Zied Marrakchi. Physical Design Exploration of 3D Tree-based FPGA Architecture. GLSVLSI'13 - The 23rd ACM international conference on Great lakes symposium on VLSI, May 2013, Paris, France. pp.335-336, ⟨10.1145/2483028.2483130⟩. ⟨hal-00873292⟩

Arwa Ben Dhia, Saif Ur Rehman, Adrien Blanchardon, Lirida Naviner, Mounir Benabdenbi, et al.. A Defect-tolerant Cluster in a Mesh SRAM-based FPGA. International Conference on Field-Programmable Technology (FPT), Dec 2013, Kyoto, Japan. pp.434-437, ⟨10.1109/FPT.2013.6718407⟩. ⟨hal-00987365⟩

Vinod Pangracious, Habib Mehrez, Zied Marrakchi. Architecture Level TSV Count Minimization Methodology for 3D Tree-based FPGA. Cool Chips XVI, Apr 2013, Yokohama, Japan. pp.1-3, ⟨10.1109/CoolChips.2013.6547925⟩. ⟨hal-00873268⟩

Vinod Pangracious, Habib Mehrez, Zied Marrakchi. Designing 3D tree-based FPGA: Interconnect Optimization and Thermal Analysis. NEWCAS'13 - IEEE 11th International Conference on New Circuits and Systems, Jun 2013, Paris, France. pp.1-4, ⟨10.1109/NEWCAS.2013.6573575⟩. ⟨hal-00873274⟩

Qingshan Tang, Matthieu Tuna, Zied Marrakchi, Habib Mehrez. Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist. The 9th International Symposium on Applied Reconfigurable Computing, ARC 2013, Mar 2013, Los Angeles, United States. pp.221, ⟨10.1007/978-3-642-36812-7_24⟩. ⟨hal-00818279⟩

Qingshan Tang, Matthieu Tuna, Habib Mehrez. Routing algorithm for multi-FPGA based systems using multi-point physical tracks. RSP 2013 - 24th IEEE International Symposium on Rapid System Prototyping, Oct 2013, Montreal, Canada. pp.2-8, ⟨10.1109/RSP.2013.6683951⟩. ⟨hal-00934833⟩

Jung Kyu Chae, Paul Mougeat, Jean-Arnaud Francois, Roselyne Chotin-Avot, Habib Mehrez. A formalism of the specifications for library development. IEEE International System-on-Chip Conference, Sep 2013, Erlangen, Germany. pp.307-312, ⟨10.1109/SOCC.2013.6749706⟩. ⟨hal-00953500⟩

Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. Lightweight and Compact Solutions for Secure Reconfiguration of FPGAs. International Conference on Reconfigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. pp.1-4, ⟨10.1109/ReConFig.2013.6732304⟩. ⟨hal-01216543⟩

Jung Kyu Chae, Severine Bertrand, Pierre-Francois Ollagnon, Paul Mougeat, Jean-Arnaud Francois, et al.. Efficient State-Dependent Power Model for Multi-bit Flip-Flop Banks. IEEE International Midwest Symposium on Circuits and Systems, Aug 2013, Columbus, United States. pp.461-464, ⟨10.1109/MWSCAS.2013.6674685⟩. ⟨hal-00913885⟩

Vinod Pangracious, Habib Mehrez, Zied Marrakchi. Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology. IEEE International 3D Systems Integration Conference (3DIC), 2013, Oct 2013, San Francisco, CA, United States. pp.1-8, ⟨10.1109/3DIC.2013.6702342⟩. ⟨hal-00944767⟩

Vinod Pangracious, Zied Marrakchi, Emna Amouri, Habib Mehrez. Performance analysis and optimization of high density tree-based 3d multilevel FPGA. Reconfigurable Computing: Architectures, Tools and Applications, Mar 2013, Los Angeles, CA, United States. pp.197-209, ⟨10.1007/978-3-642-36812-7_19⟩. ⟨hal-00872757⟩

Jung Kyu Chae, Paul Mougeat, Jean-Arnaud François, Roselyne Chotin-Avot, Habib Mehrez. Formalisme de la spécification de la plateforme de conception pour le développement de la bibliothèque. Journees Nationales du Reseau Doctoral de Micro-electronique, 2013, Grenoble, France. pp.1-4. ⟨hal-01215668⟩

Emna Amouri, Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Zied Marrakchi. Efficient Multilevel Interconnect Topology for Cluster-based Mesh FPGA Architecture. ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. pp.1-6, ⟨10.1109/ReConFig.2013.6732282⟩. ⟨hal-00987368v2⟩

Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. Protecting FPGA Bitstreams Using Authenticated Encryption. 11th IEEE International Conference of New Circuits and Systems (NEWCAS), Jun 2013, Paris, France. pp.1-4, ⟨10.1109/NEWCAS.2013.6573635⟩. ⟨hal-01017823v2⟩

Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. Improved Method for Parallel AES-GCM Cores Using FPGAs. ReConFig 2013 - International Conference on Reconfigurable Computing and FPGAs, Dec 2013, Cancun, Mexico. pp.1-4, ⟨10.1109/ReConFig.2013.6732299⟩. ⟨hal-01160904⟩

Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. High Speed Authenticated Encryption for Slow Changing Key Applications Using Reconfigurable Devices. Wireless Days (WD), 2013 IFIP, Nov 2013, Valencia, Spain. pp.1 - 6, ⟨10.1109/WD.2013.6686460⟩. ⟨hal-01017858v2⟩

Nidhameddine Belhadj, Najmeddine Bahri, M. Ali Ben Ayed, Zied Marrakchi, Habib Mehrez. Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC. 2013 10th International Multi-Conference on Systems, Signals & Devices (SSD), Mar 2013, Hammamet, Tunisia. ⟨10.1109/SSD.2013.6564040⟩. ⟨hal-01797203⟩

Fatma Hamzaoui, Roselyne Chotin-Avot, Patricia Renault, Habib Mehrez, Hafedh Belmabrouk, et al.. Synthesis and Optimization of Quantum Boolean Circuit Using the Truth Table Method. International Workshop on Number Theory, Codes, Cryptography and Communication Systems (NTCCCS), Apr 2012, Oujda, Morocco. pp.192-197. ⟨hal-01265626⟩

Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez. Générateur d'Architecture de FPGA. Colloque GDR SOC-SIP, Jun 2012, Paris, France. pp.1-3. ⟨hal-00987369⟩

Alp Kilic, Zied Marrakchi, Matthieu Tuna, Habib Mehrez. A Logic Sharing Synthesis Tool for Mutually Exclusive Applications. Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2012 7th International Conference on, May 2012, Gammarth, Tunisia. pp.1 - 6, ⟨10.1109/DTIS.2012.6232984⟩. ⟨hal-00827442⟩

Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. Efficient Parallel-Pipelined GHASH for Message Authentication. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2012), Dec 2012, Cancun, Mexico. pp.1 - 6, ⟨10.1109/ReConFig.2012.6416742⟩. ⟨hal-01017807⟩

Qingshan Tang, Matthieu Tuna, Habib Mehrez. Design for prototyping of a parameterizable cluster-based Multi-Core System-on-Chip on a multi-FPGA board. RSP 2012 - 23rd IEEE International Symposium on Rapid System Prototyping, Oct 2012, Tampere, Finland. pp.71-77, ⟨10.1109/RSP.2012.6380693⟩. ⟨hal-00818231⟩

Mariem Turki, Habib Mehrez, Zied Marrakchi. Multi-FPGA Prototyping Environment: Large Benchmark Generation and Signals Routing. 2014 International Conference on Reconfigurable computing and FPGA, Dec 2012, Cancun, Mexico. ⟨10.1109/ReConFig.2012.6416765⟩. ⟨hal-01058039⟩

Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. The Effect of S-box Design on Pipelined AES Using FPGAs. Colloque GDR SOC-SIP, Jun 2012, Paris, France. pp.1-4. ⟨hal-01265624⟩

Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez. Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools. ISQED 2011 - 12th International Symposium on Quality Electronic Design, Mar 2011, Santa Clara, CA, United States. pp.502-507, ⟨10.1109/ISQED.2011.5770774⟩. ⟨hal-01265627⟩

Umer Farooq, Husain Parvez, Emna Amouri, Habib Mehrez, Zied Marrakchi. Exploring the Effect of LUT and Arity Size on a Tree-based Application Specific Inflexible FPGA. International conference on Design & Technology of Integrated Systems (DTIS), Apr 2011, Athens, Greece. pp.1-6, ⟨10.1109/DTIS.2011.5941426⟩. ⟨hal-01284605⟩

Fatma Hamzaoui, Roselyne Chotin-Avot, Mohsen Machhout, Habib Mehrez, Hafedh Belmabrouk. Quantum circuits design and simulation. The First International Conference on "Research to Applications & Markets" (RAM 2011), Jun 2011, Monastir, Tunisia. pp.115-115. ⟨hal-01265628⟩

Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez. Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA. The 7th International Symposium on Applied Reconfigurable Computing, Mar 2011, Belfast, United Kingdom. pp.218-229, ⟨10.1007/978-3-642-19475-7_23⟩. ⟨hal-01286069⟩

Emna Amouri, Zied Marrakchi, Habib Mehrez. Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA. 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2011, Jun 2011, Montpellier, France. pp.1-4, ⟨10.1109/ReCoSoC.2011.5981528⟩. ⟨hal-01286036⟩

Fatma Hamzaoui, Besma Othmani, Roselyne Chotin-Avot, Mohsen Machhout, Hafedh Belmabrouk, et al.. Modélisation et simplification de circuits quantiques. Materiaux 2010, Nov 2010, Mahdia, Tunisia. pp.2-2. ⟨hal-01265629⟩

Umer Farooq, Zied Marrakchi, Habib Mehrez. A New Datapath-Oriented Tree-based FPGA Architecture. IEEE International Conference on Microelectronics (ICM), Dec 2010, Cairo, Egypt. pp.403-406, ⟨10.1109/ICM.2010.5696172⟩. ⟨hal-01292069⟩

Zied Marrakchi, Husain Parvez, Alp Kilic, Habib Mehrez, Hmaied Marrakchi. On the optimization of FPGA area depending on target applications. APCCAS 2010 - IEEE Asia Pacific Conference on Circuits and Systems, Dec 2010, Kuala Lumpur, Malaysia. pp.308--311, ⟨10.1109/APCCAS.2010.5774849⟩. ⟨hal-01372836⟩

Mariem Turki, Mohamed Abid, Zied Marrakchi, Habib Mehrez. Routability driven placement for mesh-based FPGA architecture. IDT 2010 - 5th International Design and Test Workshop, Dec 2010, Abu Dhabi, United Arab Emirates. pp.85--90, ⟨10.1109/IDT.2010.5724414⟩. ⟨hal-01372834⟩

Ludovic Noury, Habib Mehrez. A flexible realtime system for broadband time-frequency analysis in 130 NM CMOS. ICECS 2010 - 17th IEEE International Conference on Electronics, Circuits and Systems, Dec 2010, Athens, Greece. pp.251--254, ⟨10.1109/ICECS.2010.5724501⟩. ⟨hal-01372835⟩

Emna Amouri, Zied Marrakchi, Habib Mehrez. Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA. APCCAS 2010 - IEEE Asia Pacific Conference on Circuits and Systems, Dec 2010, Kuala Lumpur, Malaysia. pp.296--299, ⟨10.1109/APCCAS.2010.5774878⟩. ⟨hal-01372837⟩

Zied Guitouni, Roselyne Chotin-Avot, Mohsen Machhout, Habib Mehrez, Rached Tourki. Design and FPGA Implementation of Modular Multiplication Methods Using Cellular Automata. DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Mar 2010, Hammamet, Tunisia. pp.1-5, ⟨10.1109/DTIS.2010.5487586⟩. ⟨hal-01265630⟩

Husain Parvez, Zied Marrakchi, Habib Mehrez. Heterogeneous-ASIF: An Application Specific Inflexible FPGA using Heterogeneous logic blocks. FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2010, Monterey, California, United States. pp.290-290, ⟨10.1145/1723112.1723181⟩. ⟨hal-01290706⟩

Husain Parvez, Zied Marrakchi, Habib Mehrez. Application Specific FPGA Using Heterogeneous Logic Blocks. ARC International Symposium on Applied Reconfigurable Computing, Mar 2010, Bangkok, Thailand. pp.92-109, ⟨10.1007/978-3-642-12133-3_11⟩. ⟨hal-01290708⟩

Zied Marrakchi, Umer Farooq, Hayder Mrabet, Habib Mehrez. Comparison of Tree-Based and Mesh-Based Coarse-Grained FPGA Architectures. ICM International Conference on Microelectronics, Dec 2009, Marrakech, Morocco. pp.248-251, ⟨10.1109/ICM.2009.5418640⟩. ⟨hal-01295097⟩

Husain Parvez, Zied Marrakchi, Habib Mehrez. ASIF: Application Specific Inflexible FPGA. ICFPT International Conference on Field-Programmable Technology, Dec 2009, Sydney, Australia. pp.112-119, ⟨10.1109/FPT.2009.5377657⟩. ⟨hal-01295122⟩

Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez. Placement and Routing Techniques to Improve Delay Balance of WDDL Netlist in MFPGA. IEEE International Conference on Electronics, Circuits, and Systems - ICECS 2009, Dec 2009, Hammamet, Tunisia. pp.791-794, ⟨10.1109/ICECS.2009.5410774⟩. ⟨hal-01294427⟩

Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez. Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. ReConFig International Conference on Reconfigurable Computing and FPGAs 2009, Dec 2009, Cancun, Mexico. pp.201-206, ⟨10.1109/ReConFig.2009.44⟩. ⟨hal-01295098⟩

Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez. A New Tree-based coarse-grained FPGA Architecture. IEEE International Conference on PhD. Research in MicroElectronics, PRIME'09, Jul 2009, Cork, Ireland. pp.48-51, ⟨10.1109/RME.2009.5201347⟩. ⟨hal-01298010⟩

Hayder Mrabet, Husain Parvez, Zied Marrakchi, Habib Mehrez. Automatic Layout Generator of Domain Specific FPGA:. ICM International Conference on Microelectronics, Dec 2008, Sharjah, United Arab Emirates. pp.183-186, ⟨10.1109/ICM.2008.5393493⟩. ⟨hal-01299216⟩

Husain Parvez, Hayder Mrabet, Habib Mehrez. Generic Techniques and CAD tools for automated generation of FPGA Layout. PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Jun 2008, Istanbul, Turkey. pp.141-144, ⟨10.1109/RME.2008.4595745⟩. ⟨hal-01301526⟩

Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez. Arithmetic Data path Optimization using Borrow-Save Representation. ISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI, Apr 2008, Montpellier, France. pp.4-9, ⟨10.1109/ISVLSI.2008.29⟩. ⟨hal-01265632⟩

Umer Farooq, Zied Marrakchi, Hayder Mrabet, Habib Mehrez. The Effect of LUT and Cluster Size on a Tree based FPGA Architecture. ReConFig International Conference on Reconfigurable Computing and FPGAs, Dec 2008, Cancun, Mexico. pp.115-120, ⟨10.1109/ReConFig.2008.28⟩. ⟨hal-01299218⟩

Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez. Efficient Tree Topology for FPGA Interconnect Network. GLSVLSI ACM Great Lakes Symposium on VLSI, May 2008, Orlando, Florida, United States. pp.321-326, ⟨10.1145/1366110.1366186⟩. ⟨hal-01301523⟩

Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez, Alix Munier-Kordon. Automatic Allocation of Redundant Operators in Arithmetic Data path Optimization. DASIP IEEE International Conference on Design and Architectures for Signal and Image Processing, Nov 2008, Bruxelles, Belgium. pp.176-183. ⟨hal-01265631⟩

Husain Parvez, Zied Marrakchi, Umer Farooq, Habib Mehrez. A New Coarse-grained FPGA Architecture Exploration Environment. ICFPT International Conference on Field-Programmable Technology, Dec 2008, Taipei, Taiwan. pp.285-288, ⟨10.1109/FPT.2008.4762399⟩. ⟨hal-01301527⟩

Husain Parvez, Zied Marrakchi, Habib Mehrez. Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-grained FPGAs. ReConFig International Conference on Reconfigurable Computing and FPGAs, Dec 2008, Cancun, Mexico. pp.121-126, ⟨10.1109/ReConFig.2008.53⟩. ⟨hal-01301529⟩

Sophie Belloeil, Damien Dupuis, Christian Masson, Jean-Paul Chaput, Habib Mehrez. Stratus: A procedural circuit description language based upon Python. ICM International Conference on Microelectronics, Dec 2007, Cairo, Egypt. pp.275-278, ⟨10.1109/ICM.2007.4497707⟩. ⟨hal-01305970⟩

Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez. Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. NoC ACM/IEEE International Symposium on Networks-on-Chip, May 2007, Princeton, United States. pp.243-252, ⟨10.1109/NOCS.2007.27⟩. ⟨hal-01305788⟩

Sophie Belloeil, Roselyne Chotin-Avot, Habib Mehrez. Data Path Optimization using Redundant Arithmetic and Pattern Matching. Workshop on Design and Architectures for Signal and Image Processing (DASIP'2007), Nov 2007, Grenoble, France. pp.281-288. ⟨hal-01265633⟩

Ludovic Noury, François Durbin, Habib Mehrez, André Tissot. A Generic ASIC Architecture for Real Time Time-Frequency Analysis of Non-stationary Large Bandwidth Signals. IMTC IEEE Instrumentation and Measurement Technology Conference, May 2007, Warsaw, Poland. pp.1-5, ⟨10.1109/IMTC.2007.379468⟩. ⟨hal-01311481⟩

Ludovic Noury, Habib Mehrez, François Durbin, André Tissot. A Cascadable ASIC Prototype for Real Time Time-Frequency Analysis. MWSCAS Midwest Symposium on Circuits and Systems, Aug 2007, Montreal, Canada. pp.690-693, ⟨10.1109/MWSCAS.2007.4488673⟩. ⟨hal-01311484⟩

Zied Marrakchi, Hayder Mrabet, Grégory Souffleteau, Christian Masson, Habib Mehrez. A Routability Driven Partitioning and Detailed Placement Approach for Multilevel Hierarchical FPGA. FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2007, Monterey, Californie, United States. pp.225-225. ⟨hal-01311525⟩

Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez. Efficient Mesh of Tree Interconnect for FPGA Architecture. ICFPT International Conference on Field-Programmable Technology, Dec 2007, Kitakyushu, Japan. pp.269-272, ⟨10.1109/FPT.2007.4439263⟩. ⟨hal-01305972⟩

Sophie Belloeil, Jean-Paul Chaput, Roselyne Chotin-Avot, Christian Masson, Habib Mehrez. Stratus : Un environnement de développement de circuits. JP CNFM Journées pédagogiques du CNFM, 2006, Saint-Malo, France. pp.57-61. ⟨hal-01265634⟩

Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot. Implementation of Scalable Embedded FPGA for SOC. DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Sep 2006, Tunis, Tunisia. pp.74-77, ⟨10.1109/DTIS.2006.1708687⟩. ⟨hal-01338253⟩

Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez. Performances Improvement of FPGA using Novel Multilevel Hierarchical Interconnection Structure. ICCAD IEEE/ACM International Conference on Computer-Aided Design, Nov 2006, San Jose, California, United States. pp.675-679, ⟨10.1109/ICCAD.2006.320012⟩. ⟨hal-01338460⟩

Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez, André Tissot. Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. ReCoSoC 2006 - 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Jul 2006, Montpellier, France. pp.117--123. ⟨hal-01372838⟩

Zied Marrakchi, Hayder Mrabet, Habib Mehrez. Evaluation of Hierarchical FPGA partitioning methodologies based on architecture Rent Parameter. PRIME IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Jun 2006, Otranto, Italy. pp.85-88, ⟨10.1109/RME.2006.1689902⟩. ⟨hal-01338243⟩

Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez. A multilevel hierarchical interconnection structure for FPGA. FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2006, Monterey, California, United States. pp.225-225, ⟨10.1145/1117201.1117239⟩. ⟨hal-01338215⟩

Zied Marrakchi, Hayder Mrabet, Habib Mehrez. Configuration tools for a new multilevel hierarchical FPGA. FPGA ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Feb 2006, Monterey, California, United States. pp.229-229, ⟨10.1145/1117201.1117248⟩. ⟨hal-01338217⟩

Zied Marrakchi, Hayder Mrabet, Habib Mehrez. A new Multilevel Hierarchical MFPGA and its suitable configuration tools. ISVLSI IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, Mar 2006, Karlsruhe, Germany. pp.263-268, ⟨10.1109/ISVLSI.2006.6⟩. ⟨hal-01338233⟩

Zied Marrakchi, Hayder Mrabet, Habib Mehrez. Performances comparison between Multilevel hierarchical and Mesh FPGA. DTIS IEEE International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Sep 2006, Tunis, Tunisia. pp.166-171, ⟨10.1109/DTIS.2006.1708712⟩. ⟨hal-01338430⟩

Sophie Belloeil, Habib Mehrez. Optimisation de chemins de données par l'utilisation de l'arithmétique redondante. JNRDM 2005 - 8èmes Journées Nationales du Réseau Doctoral en Microélectronique, May 2005, Paris, France. pp.268-270. ⟨hal-01418345⟩

Ana Belen Abril Garcia, Habib Mehrez, Frédéric Pétrot, Jean Gobert, Carolina Miro. Energy Estimation and Optimisation of Embedded Systems using Cycle Accurate Simulation. FTFC 2005 - 5èmes Journées d'études Faible Tension Faible Consommation, May 2005, Paris, France. pp.29-32. ⟨hal-01418349⟩

Zied Marrakchi, Hayder Mrabet, Habib Mehrez. Hierarchical FPGA clustering to improve routability. PRIME 2005 - IEEE Conference on Ph.D. Research in MicroElectronics and Electronics, Jul 2005, Lausanne, Switzerland. pp.165-168, ⟨10.1109/RME.2005.1543029⟩. ⟨hal-01419664⟩

Zied Marrakchi, Hayder Mrabet, Habib Mehrez. Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation. ReConFig 2005 - International Conference on Reconfigurable Computing and FPGAs, Sep 2005, Puebla City, Mexico. pp.21-25, ⟨10.1109/RECONFIG.2005.23⟩. ⟨hal-01372839⟩

Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot. Implementation of Scalable Embedded FPGA for SOC. ReCoSoC 2005 - 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Jun 2005, Montpellier, France. pp.74-77. ⟨hal-01419656⟩

Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot. Automatic Layout of Scalable Embedded Field Programmable Gate Array. ICEEC 2004 - International Conference on Electrical Electronic and Computer Engineering, Sep 2004, Cairo, Egypt. pp.469-472, ⟨10.1109/ICEEC.2004.1374502⟩. ⟨hal-01521128⟩

Ludovic Noury, Habib Mehrez, François Durbin, André Tissot. Use of multiple numeration systems for architecture and design of a high performance FIR filter netlist generator. ICM 2004 - 16th International Conference on Microelectronics, Dec 2004, Tunis, Tunisia. pp.547-550, ⟨10.1109/ICM.2004.1434721⟩. ⟨hal-01498583⟩

Ludovic Noury, Habib Mehrez. Générateur de netlist de filtres numériques RIF optimisés. JNRDM 2004 - 7èmes Journées Nationales du Réseau Doctoral en Microélectronique, May 2004, Marseille, France. pp.451-453. ⟨hal-01521112⟩

Roselyne Chotin-Avot, Habib Mehrez. Hardware implementation of discrete stochastic arithmetic. 6th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'03), 2003, Poznan, Poland. pp.57-64. ⟨hal-01267471⟩

Roselyne Chotin, Habib Mehrez. Implantation matérielle d'une méthode de contrôle des erreurs d'arrondi de calcul. Troisième colloque du GDR CAO de circuits et systèmes intégrés, 2002, Paris, France. pp.63-66. ⟨hal-01265636⟩

Roselyne Chotin, Habib Mehrez. Une unité de calcul flottant utilisant l'arithmétique stochastique. Vèmes Journées Nationales du Réseau Doctoral de Micro-électronique (JNRDM'2002), 2002, Grenoble, France. pp.217-218. ⟨hal-01265637⟩

Roselyne Chotin, Habib Mehrez. Hardware implementation of the CESTAC method. 10th GAMM - IMACS International Symposium on Scientific Computing Computer Arithmetic and Validated Numerics (SCAN'2002), Sep 2002, Paris, France. pp.162-162. ⟨hal-01265638⟩

Roselyne Chotin, Habib Mehrez. Hardware implementation of a method to control round-off errors. 6th WSEAS International Multiconference on Circuits Systems Communications and Computers (CSCC'2002), Jul 2002, Rethymnon, Greece. pp.157-162. ⟨hal-01265639⟩

Roselyne Chotin, Habib Mehrez. A Floating-Point Unit using stochastic arithmetic compliant with the IEEE-754 standard. 9th IEEE International Conference on Electronics Circuits and Systems (ICECS'2002), Sep 2002, Dubrovnik, Croatia. pp.603-606, ⟨10.1109/ICECS.2002.1046241⟩. ⟨hal-01265640⟩

Garcia Ana-Belén Abril, Jean Gobert, Thomas Dombek, Habib Mehrez, Frédéric Pétrot. Energy Estimations in High Level Cycle-Accurate Descriptions of Embedded Systems. The 5th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'2002), Apr 2002, Brno, Czech Republic. pp.228-235. ⟨hal-01544286⟩

Yannick Dumonteix, Yann Bajot, Habib Mehrez. A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic. IEEE International Symposium on Circuits and Systems (ISCAS'2001), May 2001, Sydney, Australia. pp.878-881, ⟨10.1109/ISCAS.2001.922378⟩. ⟨hal-01571016⟩

Roselyne Chotin, Yannick Dumonteix, Habib Mehrez. Use of Redundant Arithmetic on Architecture and Design of a High Performance DCT Macro-bloc Generator. 15th Design of Circuits and Integrated Systems Conference (DCIS), 2000, Montpellier, France. pp.428-433. ⟨hal-01265641⟩

Yann Bajot, Habib Mehrez. GSM EFR Vocoder on a Configurable DSP Core, A Quantitative Analysis. International Conference On Signal Processing Applications and Technologies (ICSPAT 2000), Oct 2000, Dallas, Texas, United States. pp.1-6. ⟨hal-01572597⟩

Yannick Dumonteix, Habib Mehrez. A family of redundant multipliers dedicated to fast computation for signal processing. IEEE International Symposium on Circuits and Systems (ISCAS 2000), May 2000, Geneva, Switzerland. pp.325-328, ⟨10.1109/ISCAS.2000.857430⟩. ⟨hal-01573053⟩

Yannick Dumonteix, Hassan Aboushady, Habib Mehrez, Marie-Minerve Rosset-Louërat. Low-power Comb Decimation Filter Using Polyphase Decomposition For Mono-bit Sigma-Delta Analog-to-Digital Converters. International Conference On Signal Processing Applications and Technologies (ICSPAT 2000), Oct 2000, Dallas, Texas, United States. pp.432-435. ⟨hal-01572598⟩

Hassan Aboushady, Yannick Dumonteix, Marie-Minerve Rosset-Louërat, Habib Mehrez. Efficient Polyphase Decomposition of Comb Decimation Filters in Sigma-Delta Analog-to-Digital Converters. 43rd IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2000), Aug 2000, Lansing, MI, United States. pp.432-435, ⟨10.1109/MWSCAS.2000.951676⟩. ⟨hal-01572708⟩

Yann Bajot, Habib Mehrez. A Macro-Block Based Methodology for ASIP Core Design. International Conference On Signal Processing Applications and Technologies (ICSPAT'99), 1999, Orlando, FL, United States. pp.302-305. ⟨hal-01574075⟩

Mourad Aberbour, Habib Mehrez. Architecture and design Methodology of the RBF-DDA Neural Network. IEEE International Symposium on Circuits and Systems (ISCAS'98), May 1998, Monterey, CA, United States. pp.199-202, ⟨10.1109/ISCAS.1998.703974⟩. ⟨hal-01618369⟩

Mourad Aberbour, Habib Mehrez, François Durbin, Thierry Garié, André Tissot. System Level Design of a Pattern Recognition System Based on the Gabor Wavelets. IEEE-SP Conference on Time-Frequency Time-Scale Analysis (TFTS'98), Oct 1998, Pittsburgh, PA, United States. pp.237-240, ⟨10.1109/TFSA.1998.721405⟩. ⟨hal-01618062⟩

Mourad Aberbour, Habib Mehrez, François Durbin, Thierry Garié, André Tissot. Algorithms and VLSI Architectures for Pattern Recognition Based on the Gabor Wavelets. International Conference on Signal Processing Applications and Technology (ICSPAT'98), Sep 1998, Toronto, Canada. pp.1455-1459. ⟨hal-01618074⟩

Mourad Aberbour, F. Ahmad, Habib Mehrez. A Hardware Implementation of an RBF Neural Network : Architecture and Design Methodology. International Conference on Signal Processing and Technology 97, Sep 1997, San Diego, CA, United States. pp.199 - 202. ⟨hal-01627996⟩

El Housseine Rejouan, Habib Mehrez. Automatic Generation Of Self Testing ROM. 4th Mixed Design of Integrated Circuits and Systems (MIXDES'1997), Jun 1997, Poznan, Poland. pp.1-5. ⟨hal-01627800⟩

Karim Moussa Ali Abdellatif, Roselyne Chotin-Avot, Zied Marrakchi, Habib Mehrez, Qingshan Tang. Towards high performance GHASH for pipelined AES-GCM using FPGAs. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '14, Feb 2014, Monterey, CA, United States. ACM, pp.242-242, 2014, ⟨10.1145/2554688.2554709⟩. ⟨hal-00969267⟩

Vinod Pangracious, Zied Marrakchi, Habib Mehrez. Three-Dimensional Design Methodologies for Tree-based FPGA Architecture. Springer, 350, 2015, Lecture Notes in Electrical Engineering, 978-3-319-19173-7. ⟨10.1007/978-3-319-19174-4⟩. ⟨hal-01369142⟩

Umer Farooq, Zied Marrakchi, Habib Mehrez. Tree Based Heterogeneous FPGA Architectures, Application Specific Exploration and Optimization. Springer, 2012, 978-1-4614-3593-8. ⟨10.1007/978-1-4614-3594-5⟩. ⟨hal-01272904⟩

Husain Parvez, Habib Mehrez. Application-Specific Mesh-based Heterogeneous FPGA Architectures. Springer, 202, 2011, 978-1-4419-7927-8. ⟨10.1007/978-1-4419-7928-5⟩. ⟨hal-01293873⟩

Yann Bajot, Habib Mehrez. Les systèmes de traitement numérique du signal. [Rapport de recherche] lip6.2001.021, LIP6. 2001. ⟨hal-02545594⟩