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GC
Guy Cathébras
2
Documents
Identifiants chercheurs
guy-cathebras- IdRef : 120895994
Présentation
Publications
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Design of a Low Jitter Multi-Phase Realigned PLL in Submicronic CMOS TechnologyISCAS'07: IEEE International Symposium on Circuits and Systems, May 2007, New Orleans, LA, USA, pp.2490-2493, ⟨10.1109/ISCAS.2007.378744⟩
Communication dans un congrès
lirmm-00265700v1
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Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICsNadine Azémard, Philippe Maurine, Johan Vounckx. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 4148/2006, Springer Berlin / Heidelberg, pp.458-467, 2006, Lecture Notes in Computer Science, 978-3-540-39094-7. ⟨10.1007/11847083_44⟩
Chapitre d'ouvrage
lirmm-00109058v1
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