Giorgio Di Natale
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Documents
Présentation
Giorgio Di Natale received the PhD in Computer Engineering from the Politecnico di Torino in 2003. He is director of research for the National Research Center of France at the TIMA laboratory in Grenoble.
His research interests include hardware security and trust, secure circuits design and test, reliability evaluation and fault tolerance, software implemented hardware fault tolerance, and VLSI testing.
Publications
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Using Outliers to Detect Stealthy Hardware Trojan Triggering?IVSW: International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, France
Communication dans un congrès
lirmm-01347119v1
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Duplication-based Concurrent Detection of Hardware Trojans in Integrated CircuitsTRUDEVICE, Nov 2016, Barcelona, Spain
Communication dans un congrès
lirmm-01385551v1
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Hardware Trust through Layout Filling: a Hardware Trojan Prevention TechniqueISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, United States. pp.254-259, ⟨10.1109/ISVLSI.2016.22⟩
Communication dans un congrès
lirmm-01346529v1
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Hardware Trojan Prevention using Layout-Level Design ApproachECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. ⟨10.1109/ECCTD.2015.7300093⟩
Communication dans un congrès
lirmm-01234072v1
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New Testing Procedure for Finding Insertion Sites of Stealthy Hardware TrojansDATE 2015 - 18th Design, Automation and Test in Europe Conference and Exhibition, Mar 2015, Grenoble, France. pp.776-781, ⟨10.7873/DATE.2015.1102⟩
Communication dans un congrès
lirmm-01141619v1
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A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware TrojansIOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. pp.49-54, ⟨10.1109/IOLTS.2014.6873671⟩
Communication dans un congrès
lirmm-01025275v1
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Detection and Prevention of Hardware Trojan through Logic TestingTRUDEVICE, Nov 2016, Barcelona, Spain. , 4th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, Manufacturing test of secure devices / Reverse engineering countermeasures / Other topics, pp.#33, 2016, Posters IV
Poster de conférence
lirmm-01430007v1
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