Giorgio Di Natale
120
Documents
Présentation
Giorgio Di Natale received the PhD in Computer Engineering from the Politecnico di Torino in 2003. He is director of research for the National Research Center of France at the TIMA laboratory in Grenoble.
His research interests include hardware security and trust, secure circuits design and test, reliability evaluation and fault tolerance, software implemented hardware fault tolerance, and VLSI testing.
Publications
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Encryption-Based Secure JTAGDDECS 2019 - 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2019, Cluj-Napoca, Romania. pp.1-6, ⟨10.1109/DDECS.2019.8724654⟩
Communication dans un congrès
hal-02149061v1
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A Comprehensive Approach to a Trusted Test InfrastructureIVSW 2019 - 4th IEEE International Verification and Security Workshop, Jul 2019, Rhodes, Greece. pp.43-48, ⟨10.1109/IVSW.2019.8854428⟩
Communication dans un congrès
lirmm-02306980v1
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Stream Cipher Based Encryption in IEEE Test StandardsTRUDEVICE 2019 - 8th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, May 2019, Baden Baden, Germany
Communication dans un congrès
hal-02506743v1
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Providing Confidentiality and Integrity in Ultra Low Power IoT DevicesDTIS 2019 - 14th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Apr 2019, Mykonos, Greece. ⟨10.1109/DTIS.2019.8735090⟩
Communication dans un congrès
hal-02166920v1
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Does stream cipher-based scan chains encryption really prevent scan attacks?TRUDEVICE Workshop, Mar 2018, Dresden, Germany
Communication dans un congrès
lirmm-01867286v1
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A new secure stream cipher for scan chain encryption3rd IEEE International Verification and Security Workshop (IVSW 2018), Jul 2018, Platja d’Aro, Spain. pp.68-73, ⟨10.1109/IVSW.2018.8494852⟩
Communication dans un congrès
lirmm-01867256v1
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Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault modelFDTC: Fault Diagnosis and Tolerance in Cryptography, Sep 2018, Amsterdam, Netherlands. pp.1-6, ⟨10.1109/FDTC.2018.00009⟩
Communication dans un congrès
emse-01856008v1
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Encryption of test data: which cipher is better?PRIME: PhD Research in Microelectronics and Electronics, Jul 2018, Prague, Czech Republic. pp.85-88, ⟨10.1109/PRIME.2018.8430366⟩
Communication dans un congrès
lirmm-01867249v1
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Assessing Body Built-In Current Sensors for Detection of Multiple Transient FaultsESREF 2018 - European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Oct 2018, Aalborg, Denmark
Communication dans un congrès
hal-04457522v1
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The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacksIOLTS: International On-Line Testing Symposium, Jul 2018, Platja d’Aro, Spain. pp.214-219, ⟨10.1109/IOLTS.2018.8474230⟩
Communication dans un congrès
emse-01856000v1
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SI ECCS: SECure context saving for IoT devicesDTIS 2018 - 13th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, Apr 2018, Taormina, Italy. ⟨10.1109/DTIS.2018.8368561⟩
Communication dans un congrès
hal-01740173v1
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Scan Chain EncryptionDOCTIS: Journée des Doctorants de l’école doctorale I2S, 2017, Montpellier, France
Communication dans un congrès
lirmm-01867277v1
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Experimentations on scan chain encryption with PRESENTIVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.45-50, ⟨10.1109/IVSW.2017.8031543⟩
Communication dans un congrès
lirmm-01699258v1
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Hacking the Control Flow error detection mechanismIVSW: International Verification and Security Workshop, Jul 2017, Thessaloniki, Greece. pp.51-56, ⟨10.1109/IVSW.2017.8031544⟩
Communication dans un congrès
lirmm-01700739v1
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Scan chain encryption for the test, diagnosis and debug of secure circuitsETS: European Test Symposium, May 2017, Limassol, Cyprus. ⟨10.1109/ETS.2017.7968248⟩
Communication dans un congrès
lirmm-01699254v1
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Duplication-based Concurrent Detection of Hardware Trojans in Integrated CircuitsTRUDEVICE, Nov 2016, Barcelona, Spain
Communication dans un congrès
lirmm-01385551v1
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Using Outliers to Detect Stealthy Hardware Trojan Triggering?IVSW: International Verification and Security Workshop, Jul 2016, Sant Feliu de Guixols, France
Communication dans un congrès
lirmm-01347119v1
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Hardware Trust through Layout Filling: a Hardware Trojan Prevention TechniqueISVLSI: International Symposium on Very Large Scale Integration, Jul 2016, Pittsburgh, United States. pp.254-259, ⟨10.1109/ISVLSI.2016.22⟩
Communication dans un congrès
lirmm-01346529v1
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Session-less based thermal-aware 3D-SIC test schedulingETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. ⟨10.1109/ETS.2015.7138732⟩
Communication dans un congrès
lirmm-01922990v1
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Hardware Trojan Prevention using Layout-Level Design ApproachECCTD: European Conference on Circuit Theory and Design, Aug 2015, Trondheim, Norway. ⟨10.1109/ECCTD.2015.7300093⟩
Communication dans un congrès
lirmm-01234072v1
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3D DFT Challenges and SolutionsISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.603-608, ⟨10.1109/ISVLSI.2015.11⟩
Communication dans un congrès
lirmm-01234076v1
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Multi-segment Enhanced Scan-chains for Secure ICsTRUDEVICE Workshop, Sep 2015, Saint-Malo, France
Communication dans un congrès
lirmm-01276304v1
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Validation Of Single BBICS Architecture In Detecting Multiple FaultsATS: Asian Test Symposium, Nov 2015, Mumbai, India
Communication dans un congrès
lirmm-01234067v1
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New Testing Procedure for Finding Insertion Sites of Stealthy Hardware TrojansDATE 2015 - 18th Design, Automation and Test in Europe Conference and Exhibition, Mar 2015, Grenoble, France. pp.776-781, ⟨10.7873/DATE.2015.1102⟩
Communication dans un congrès
lirmm-01141619v1
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Sensitivity to fault laser injection: a comparison between 28nm bulk and FD-SOI technologyTRUDEVICE Workshop, Sep 2015, Saint-Malo, France
Communication dans un congrès
lirmm-01234094v1
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Figure of merits of 28nm Si technologies for implementing laser attack resistant security dedicated circuitsISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.362-367, ⟨10.1109/ISVLSI.2015.76⟩
Communication dans un congrès
emse-01227138v1
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Hierarchical Secure DfTTRUDEVICE Workshop, Sep 2015, St Malo, France
Communication dans un congrès
lirmm-01234095v1
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Built-In Self-Test for Manufacturing TSV Defects before bondingVTS: VLSI Test Symposium, Apr 2014, Napa, CA, United States. ⟨10.1109/VTS.2014.6818771⟩
Communication dans un congrès
lirmm-00989682v1
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Customized Cell Detector for Laser-Induced-Fault DetectionIOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Spain. pp.37-42, ⟨10.1109/IOLTS.2014.6873669⟩
Communication dans un congrès
lirmm-01119576v1
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Laser-Induced Fault Effects in Security-Dedicated CircuitsVLSI-SoC: Very Large Scale Integration and System-on-Chip, Oct 2014, Playa del Carmen, Mexico. pp.220-240, ⟨10.1007/978-3-319-25279-7_12⟩
Communication dans un congrès
hal-01383737v1
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Layout-Aware Laser Fault Injection Simulation and Modeling: from physical level to gate levelDTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. ⟨10.1109/DTIS.2014.6850665⟩
Communication dans un congrès
lirmm-01119592v1
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Design of Bulk Built-In Current Sensors to Detect Single Event Effects and Laser-Induced Fault Injection AttemptsJoint MEDIAN–TRUDEVICE Open Forum, Sep 2014, Amsterdam, Netherlands
Communication dans un congrès
emse-01099040v1
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A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware TrojansIOLTS: International On-Line Testing Symposium, Jul 2014, Platja d'Aro, Girona, Spain. pp.49-54, ⟨10.1109/IOLTS.2014.6873671⟩
Communication dans un congrès
lirmm-01025275v1
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Simulating Laser Effects on ICs, from Physical Level to Gate Level: a comprehensive approachTRUDEVICE Workshop, May 2014, Paderborn, Germany
Communication dans un congrès
lirmm-01119614v1
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Laser attacks on integrated circuits: from CMOS to FD-SOIDTIS: Design and Technology of Integrated Systems in Nanoscale Era, May 2014, Santorin, Greece. ⟨10.1109/DTIS.2014.6850664⟩
Communication dans un congrès
emse-01099042v1
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2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT ArchitecturesISVLSI: International Symposium on Very Large Scale Integration, Jul 2014, Tampa, FL, United States. pp.386-391, ⟨10.1109/ISVLSI.2014.83⟩
Communication dans un congrès
lirmm-01119605v1
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Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS25th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2014), Sep 2014, Berlin, Germany
Communication dans un congrès
hal-03094235v1
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A BIST Method for TSVs Pre-Bond TestIDT'13: 8th IEEE International Design & Test Symposium, Dec 2013, Marrakesh, Morocco. pp.1-6, ⟨10.1109/IDT.2013.6727081⟩
Communication dans un congrès
lirmm-00989727v1
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Laser-Induced Fault SimulationEUROMICRO DSD/SEAA, Sep 2013, Santander, Spain. pp.609-614, ⟨10.1109/DSD.2013.72⟩
Communication dans un congrès
lirmm-01430807v1
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Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detectionESREF: European Symposium on Reliability of Electron devices, Failure physics and analysis, Sep 2013, Arcachon, France. pp.B3c-2 #68
Communication dans un congrès
hal-00872705v1
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A smart test controller for scan chains in secure circuitsIOLTS: International On-Line Testing Symposium, Jul 2013, Chania, Greece. pp.228-229, ⟨10.1109/IOLTS.2013.6604085⟩
Communication dans un congrès
lirmm-01430814v1
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Identification of Hardware Trojans triggering signalsFirst Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, May 2013, Avignon, France
Communication dans un congrès
lirmm-00991360v1
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A 3D IC BIST for pre-bond test of TSVs using Ring OscillatorsNEWCAS: New Circuits and Systems, Jun 2013, Paris, France. pp.001-004
Communication dans un congrès
lirmm-00838524v1
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A Bulk Built-in Sensor for Detection of Fault AttacksHOST: Hardware-Oriented Security and Trust, Jun 2013, Austin, TX, United States. pp.51-54, ⟨10.1109/HST.2013.6581565⟩
Communication dans un congrès
lirmm-01430800v1
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3D Design For Test Architectures Based on IEEE P16874th IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), Sep 2013, Anaheim, CA, United States
Communication dans un congrès
lirmm-00989717v1
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TSVs Pre-Bond Testing: a test scheme for capturing BIST responses3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Sep 2013, Anaheim, CA, United States
Communication dans un congrès
lirmm-00989707v1
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A single built-in sensor to check pull-up and pull-down CMOS networks against transient faultsPATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2013, Karlsruhe, Germany. pp.157-163, ⟨10.1109/PATMOS.2013.6662169⟩
Communication dans un congrès
lirmm-00968621v1
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Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-modeESREF: European Symposium on Reliability of Electron devices, Failure physics and analysis, Oct 2012, Cagliari, Italy
Communication dans un congrès
hal-00867864v1
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A New Scan Attack on RSA in Presence of Industrial CountermeasuresCOSADE: Constructive Side-Channel Analysis and Secure Design, May 2012, Darmstadt, Germany. pp.89-104, ⟨10.1007/978-3-642-29912-4_8⟩
Communication dans un congrès
lirmm-00719986v1
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On-Chip Comparison for Testing Secure ICsDCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.112-117
Communication dans un congrès
lirmm-00795205v1
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Is Side-Channel Analysis really reliable for detecting Hardware Trojans?DCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. pp.238-242
Communication dans un congrès
lirmm-00823477v1
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A Scan-based Attack on Elliptic Curve Cryptosystems in presence of Industrial Design-for-Testability StructuresIEEE International Symposium on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, United States. http://www.dfts.org/
Communication dans un congrès
lirmm-00744472v1
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Are Advanced DfT Structures Sufficient for Preventing Scan-Attacks?VTS'12: 30th IEEE VLSI Test Symposium, Apr 2012, Maui, Hawai, United States. pp.246-251
Communication dans un congrès
lirmm-00694536v1
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Calibrating Bulk Built-in Current Sensors for Detecting Transient FaultsColloque GDR SoC-SiP, 2012, Lyon, France
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lirmm-00715126v1
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Scan Attacks and Countermeasures in Presence of Scan Response CompactorsETS: European Test Symposium, May 2011, Trondheim, Norway. pp.19-24, ⟨10.1109/ETS.2011.30⟩
Communication dans un congrès
lirmm-00647062v1
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New side-channel attack against scan chains9th CryptArchi Workshop (2011), Jun 2011, Bochum, Germany. pp.2
Communication dans un congrès
lirmm-00648575v1
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Timing Issues for an Efficient Use of Concurrent Error Detection CodesLATW: Latin American Test Workshop, Mar 2011, Porto de Galinhas, Brazil. pp.1-6, ⟨10.1109/LATW.2011.5985933⟩
Communication dans un congrès
lirmm-00627427v1
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Power Consumption Traces Realignment to Improve Differential Power AnalysisDDECS'11: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits ans Systems, Germany. pp.201-206
Communication dans un congrès
lirmm-00592005v1
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Timing Issues of Transient Faults in Concurrent Error Detection SchemesGdR SoC-SiP'2011: Colloque national du Groupement de Recherche System-On-Chip et System-In-Package, Jun 2011, Lyon, France. http://www2.lirmm.fr/~w3mic/SOCSIP/
Communication dans un congrès
lirmm-00701798v1
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How to Sample Results of Concurrent Error Detection Schemes in Transient Fault Scenarios?RADECS: Radiation and Its Effects on Components and Systems, Sep 2011, Sevilla, Spain. pp.635-642, ⟨10.1109/RADECS.2011.6131361⟩
Communication dans un congrès
lirmm-00701776v1
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A New Bulk Built-in Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron TechnologiesDFT'2011: International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Oct 2011, Vancouver, Canada. pp.302-308, ⟨10.1109/DFT.2011.15⟩
Communication dans un congrès
lirmm-00701789v1
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New Security Threats Against Chips Containing Scan Chain StructuresHOST'11: IEEE International Symposium on Hardware-Oriented Security and Trust, San Diego, CA, United States. pp.105-110
Communication dans un congrès
lirmm-00599690v1
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Ensuring High Testability without Degrading SecurityDDECS'10: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, Vienna, Austria. pp.6
Communication dans un congrès
lirmm-00480710v1
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Evaluation of Concurrent Error Detection Techniques on the Advanced Encryption StandardIOLTS: International On-Line Testing Symposium, Jul 2010, Corfu, Greece. pp.223-228, ⟨10.1109/IOLTS.2010.5560196⟩
Communication dans un congrès
lirmm-00539232v1
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Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for DesignersDELTA'10: Fifth IEEE International Symposium on Electronic Design, Test and Application, Jan 2010, Ho Chi Minh City, Vietnam. pp.256-261
Communication dans un congrès
lirmm-00539993v1
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Waveforms re-Alignment to Improve DPA AttacksCryptArchi: Cryptographic Architectures, Jun 2010, Gif-sur-Yvette, France
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Evaluation of Concurrent Error Detection Techniques on the Advanced Encryption StandardETS: European Test Symposium, May 2010, Prague, Czech Republic
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Ensuring High Testability without Degrading SecurityETS: European Test Symposium, May 2009, Seville, Spain
Communication dans un congrès
lirmm-00407163v1
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Tutorial on Design For Testability & Digital SecurityIEEE 10th Latin American Test Workshop, 2009, Buzios, Brazil
Communication dans un congrès
lirmm-00407161v1
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Execution Time Reduction of Differential Power Analysis ExperimentsLATW'09: 10th Latin-American Test Workshop, Mar 2009, Armaçao dos Buzios, Brazil, pp.1-5, ⟨10.1109/LATW.2009.4813819⟩
Communication dans un congrès
lirmm-00367712v1
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Observability of Stuck-at-Faults with Differential Power AnalysisLATW'08: IEEE Latin American Test Workshop, Feb 2008, Mexico. pp.N/A
Communication dans un congrès
lirmm-00295498v1
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Low Cost Self-Test of Crypto-DevicesWDSN'08: 2nd Workshop on Dependable and Secure Nanocomputing, Jun 2008, Anchorage, Canada, United States. pp.41-46
Communication dans un congrès
lirmm-00295108v1
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An Integrated Validation Environment for Differential Power AnalysisDELTA: Electronic Design, Test and Applications, Jan 2008, Hong Kong, China. pp.527-532, ⟨10.1109/DELTA.2008.61⟩
Communication dans un congrès
lirmm-00407165v1
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A Reliable Architecture for Substitution Boxes in Integrated CryptographicDCIS'08: Conference on Design of Circuits and Integrated Systems, Nov 2008, pp.27-32
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lirmm-00363783v1
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An Integrated Validation Environment for Differential Power AnalysisSAME'08: Sophia-Antipolis Forum on MicroElectronics 2008, Sep 2008, Sophia-Antipolis, France
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lirmm-00363796v1
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A Reliable Architecture for the Advanced Encryption Standard13th IEEE European Test Symposium, May 2008, Verbania, Italy. pp.13-18, ⟨10.1109/ETS.2008.26⟩
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lirmm-00285868v1
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Stuck-at-Faults Test using Differential Power AnalysisLPonTR'08: Workshop on Low Power Design Impact on Test and Reliability, May 2008, Italy
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lirmm-00332529v1
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A Novel Parity Bit Scheme for SBOX in AES CircuitsIEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS), Apr 2007, Cracovie, Poland. pp.267-271, ⟨10.1109/DDECS.2007.4295295⟩
Communication dans un congrès
lirmm-00141799v1
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On-Line Self-Test of AES Hardware ImplementationsDSN'07: Workshop on Dependable and Secure Nanocomputing, Jun 2007, Edinburgh, United Kingdom
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lirmm-00163405v1
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An On-Line Fault Detection Scheme for SBoxes in Secure CircuitsIOLTS 2007 - 13th IEEE International On-Line Testing and Robust System Design Symposium, Jul 2007, Heraklion, Crete, Greece. pp.57-62, ⟨10.1109/IOLTS.2007.16⟩
Communication dans un congrès
lirmm-00163244v1
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Test and SecurityCryptArchi: Cryptographic Architectures, Jun 2007, Montpellier, France
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lirmm-00163017v1
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Encryption Techniques for Test InfrastructuresPoster de conférence lirmm-02306922v1 |
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Sécurité des moyens de test des SoCJournée thématique des GDR SoC² et Sécurité Informatique : Sécurité des SoC complexes hétérogènes – de la TEE au matériel, Sep 2018, Paris, France. 2018
Poster de conférence
lirmm-01882552v1
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SECCS: SECure Context Saving for IoT Devices12e Colloque National du GDR SoC/SiP, Jun 2018, Paris, France. 2018
Poster de conférence
hal-02042659v1
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Scan chain encryption, a countermeasure against scan attacksPHISIC: Practical Hardware Innovations in Security Implementation and Characterization, May 2018, Gardanne, France. , Workshop on Practical Hardware Innovations in Security Implementation and Characterization, 2018
Poster de conférence
lirmm-01882565v2
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Scan chain encryption in Test StandardsSURREALIST: SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices, May 2018, Bremen, Germany. , Workshop on SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices, 2018
Poster de conférence
lirmm-01882578v2
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Stream cipher-based scan encryption in test standards12e Colloque National du GDR SoC/SiP, Jun 2018, Paris, France. 2018
Poster de conférence
lirmm-01867283v1
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Sécurisation des structures de test : étude comparative11e Colloque National du GDR SoC/SiP, Jun 2017, Bordeaux, France. 2017
Poster de conférence
lirmm-01867279v1
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Scan Chain Encryption for the Test, Diagnosis and Debug of Secure CircuitsPoster de conférence lirmm-01892667v1 |
Detection and Prevention of Hardware Trojan through Logic TestingTRUDEVICE, Nov 2016, Barcelona, Spain. , 4th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, Manufacturing test of secure devices / Reverse engineering countermeasures / Other topics, pp.#33, 2016, Posters IV
Poster de conférence
lirmm-01430007v1
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tLIFTING : A Multi-level Delay-annotated Fault Simulator for Digital CircuitsDCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. , 2012
Poster de conférence
lirmm-00799892v1
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A Dependable Parallel Architecture for SBoxesReCoSoc'07: International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2007, Montpellier, France. pp.CD-ROM, 2007
Poster de conférence
lirmm-00163414v1
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Chapitre 6 : On Countermeasures Against Fault Attacks on the Advanced Encryption StandardMarc Joye and Michael Tunstall. Fault Analysis in Cryptography, Springer, pp.89-109, 2012, Information Security and Cryptography, 978-3-642-29656-0 (-7 for eBook)
Chapitre d'ouvrage
lirmm-00744671v1
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Chapter 9: Fault Detection in Crypto-devicesWei Zhang. Fault Detection, InTech, pp.177-194, 2010, 978-953-307-037-7. ⟨10.5772/213⟩
Chapitre d'ouvrage
lirmm-00437252v1
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Rapport Technique intermédiaire, Contrat TOETS CT 302, Programme CEE CATRENE2011
Autre publication scientifique
lirmm-00679018v1
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Rapport Technique de fin d'année, Contrat TOETS CT 302, Programme CEE CATRENE2011
Autre publication scientifique
lirmm-00679022v1
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TOETS CT302 - Programme CEE CATRENE - Summary Technical Report 2S-2009 - Rapport Technique de Fin d'année2010
Autre publication scientifique
lirmm-00461745v1
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Contrat TOETS CT 302 - Programme CEE CATRENE (Rapport Intermédiaire)2010
Autre publication scientifique
lirmm-00504873v1
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Test and Harware Security2008
Autre publication scientifique
lirmm-00365276v1
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Differential Power Analysis against the Miller AlgorithmRR-08021, 2008
Rapport
lirmm-00323684v1
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