Giorgio Di Natale
32
Documents
Présentation
Giorgio Di Natale received the PhD in Computer Engineering from the Politecnico di Torino in 2003. He is director of research for the National Research Center of France at the TIMA laboratory in Grenoble.
His research interests include hardware security and trust, secure circuits design and test, reliability evaluation and fault tolerance, software implemented hardware fault tolerance, and VLSI testing.
Publications
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Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope?IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2022), Apr 2022, Prague, Czech Republic. ⟨10.1109/DDECS54261.2022.9770138⟩
Communication dans un congrès
hal-03641285v1
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Alternatives to fault injections for early safety/security evaluations24th IEEE European Test Symposium (ETS 2019), May 2019, Baden Baden, Germany. ⟨10.1109/ETS.2019.8791555⟩
Communication dans un congrès
hal-02110119v1
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Rebooting Computing: The Challenges for Test and Reliability2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct 2019, Noordwijk, Netherlands. pp.8138-8143, ⟨10.1109/DFT.2019.8875270⟩
Communication dans un congrès
hal-02462194v1
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Reliability of computing systems: From flip flops to variablesIOLTS: International On-Line Testing Symposium, Jul 2017, Thessaloniki, Greece. pp.196-198, ⟨10.1109/IOLTS.2017.8046242⟩
Communication dans un congrès
lirmm-01700744v1
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SCHIFI: Scalable and flexible high performance FPGA-based fault injectorDCIS 2016 - 31st Conference on Design of Circuits and Integrated Systems, Nov 2016, Granada, Spain. ⟨10.1109/DCIS.2016.7845375⟩
Communication dans un congrès
lirmm-01700747v1
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Faster-than-at-speed execution of functional programs: An experimental analysisVLSI-SoC: Very Large Scale Integration and System-on-Chip, Sep 2016, Tallinn, Estonia. ⟨10.1109/VLSI-SoC.2016.7753581⟩
Communication dans un congrès
lirmm-01444403v1
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Cache-aware reliability evaluation through LLVM-based analysis and fault injectionIOLTS: International On-Line Testing Symposium, Jul 2016, Sant Feliu de Guixols, Spain. pp.19-22, ⟨10.1109/IOLTS.2016.7604663⟩
Communication dans un congrès
lirmm-01444619v1
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Cache- and register-aware system reliability evaluation based on data lifetime analysisVTS: VLSI Test Symposium, Apr 2016, Las Vegas, United States. ⟨10.1109/VTS.2016.7477299⟩
Communication dans un congrès
lirmm-01374569v1
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Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional ProgramsVLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability, Sep 2016, Tallinn, Estonia. pp.130-151, ⟨10.1007/978-3-319-67104-8_7⟩
Communication dans un congrès
hal-01675205v1
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Cross-layer system reliability assessment framework for hardware faultsITC: International Test Conference, Nov 2016, Fort Worth, TX, United States. ⟨10.1109/TEST.2016.7805863⟩
Communication dans un congrès
lirmm-01444774v1
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Fault injection tools based on Virtual MachinesReCoSoC: Reconfigurable and Communication-Centric Systems-on-Chip, May 2014, Montpellier, France. ⟨10.1109/ReCoSoC.2014.6861351⟩
Communication dans un congrès
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A novel Adaptive Fault Tolerant Flip-Flop Architecture based on TMRETS: European Test Symposium, May 2014, Paderborn, Germany. ⟨10.1109/ETS.2014.6847831⟩
Communication dans un congrès
lirmm-01234133v1
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LIFTING: an Open-Source Logic SimulatorDATE 2009 - Design, Automation and Test in Europe Conference and Exhibition, Apr 2009, Nice, France
Communication dans un congrès
lirmm-00407166v1
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Modularer Selbsttest und Optimierte Reparaturanalyse für Eingebettete SpeicherZUE'08: Zuverlässigkeit und Entwurf, Germany. pp.049-056
Communication dans un congrès
lirmm-00332558v1
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March Test BDN: A new March Test for Dynamic FaultsAQTR'08: Automation, Quality and Testing, Robotics, May 2008, Cluj-Napoca, Romania, pp.085-089
Communication dans un congrès
lirmm-00303528v1
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LIFTING: A Flexible Open-Source Fault SimulatorATS 2008 - 17th IEEE Asian Test Symposium, Nov 2008, Saporro, Japan. pp.035-040, ⟨10.1109/ATS.2008.17⟩
Communication dans un congrès
lirmm-00343610v1
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LIFTING: an Open-Source Logic SimulatorSAME'08: Sophia-Antipolis Forum on MicroElectronics 2008, Sep 2008, Sophia-Antipolis, France
Communication dans un congrès
lirmm-00363795v1
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Parallel Test of Identical Cores Using Test Elevators in 3D Circuits3D-Test: Testing Three-Dimensional Stacked Integrated Circuits, Nov 2010, Austin, TX, United States. IEEE, 1st International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, 2010
Poster de conférence
lirmm-00537857v1
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A Modular Memory BIST for Optimized Memory RepairIEEE Computer Society. IOLTS: International On-Line Testing Symposium, Jul 2008, Rhodes, Greece. 14th International On-Line Testing and Robust System Design Symposium, pp.171-172, 2008, ⟨10.1109/IOLTS.2008.30⟩
Poster de conférence
lirmm-00363724v1
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Cross-Layer Reliability of Computing Systemsiet - the institution of engineering and technology, pp.1-328, 2020, 978-1785617973. ⟨10.1049/PBCS057E⟩
Ouvrages
hal-02986877v1
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Design techniques to improve the resilience of computing systems: software layerCross-Layer Reliability of Computing Systems, iet - the institution of engineering and technology, pp.95-112, 2020, 978-1785617973. ⟨10.1049/PBCS057E_ch4⟩
Chapitre d'ouvrage
hal-02986855v1
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Rapport Technique intermédiaire, Contrat TOETS CT 302, Programme CEE CATRENE2011
Autre publication scientifique
lirmm-00679018v1
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Rapport Technique de fin d'année, Contrat TOETS CT 302, Programme CEE CATRENE2011
Autre publication scientifique
lirmm-00679022v1
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TOETS CT302 - Programme CEE CATRENE - Summary Technical Report 2S-2009 - Rapport Technique de Fin d'année2010
Autre publication scientifique
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Contrat TOETS CT 302 - Programme CEE CATRENE (Rapport Intermédiaire)2010
Autre publication scientifique
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