Gilles Sassatelli
148
Documents
Identifiants chercheurs
gilles-sassatelli-
0000-0002-6396-286X
- IdRef : 069998035
Présentation
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Using multifunctional standardized stack as universal spintronic technology for IoTDATE 2018 - 21st Design, Automation and Test in Europe Conference and Exhibition, Mar 2018, Dresden, Germany. pp.931-936, ⟨10.23919/DATE.2018.8342143⟩
Communication dans un congrès
hal-01864468v1
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Improving the Performance of STT-MRAM LLC through Enhanced Cache Replacement PolicyARCS: Architecture of Computing Systems, Apr 2018, Braunschweig, Germany. pp.168-180, ⟨10.1007/978-3-319-77610-1_13⟩
Communication dans un congrès
lirmm-01669254v2
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Embedded systems to high performance computing using STT-MRAMDATE 2017 - 20th Design, Automation and Test in Europe Conference and Exhibition, Mar 2017, Lausanne, Switzerland. pp.536-541, ⟨10.23919/DATE.2017.7927046⟩
Communication dans un congrès
lirmm-01548996v1
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MAGPIE: System-level Evaluation of Manycore Systems with Emerging Memory TechnologiesEMS: Emerging Memory Solutions, Mar 2017, Lausanne, Switzerland
Communication dans un congrès
lirmm-01467328v1
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OpenMP scheduling on ARM big.LITTLE architectureMULTIPROG 2016 - 9th International Workshop on Programmability and Architectures for Heterogeneous Multicores, HIPEAC, Jan 2016, Prague, Czech Republic
Communication dans un congrès
lirmm-01377630v1
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Flot automatique d’évaluation pour l’exploration d’architectures à base de mémoires non volatilesComPAS: Conférence en Parallélisme, Architecture et Système, Jul 2016, Lorient, France
Communication dans un congrès
lirmm-01345975v1
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Loop Optimization in Presence of STT-MRAM Caches: a Study of Performance-Energy TradeoffsPATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2016, Bremen, Germany. pp.162-169, ⟨10.1109/PATMOS.2016.7833682⟩
Communication dans un congrès
hal-01347354v1
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Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy ExplorationMCSoC: Embedded Multicore/Many-core Systems-on-Chip, Sep 2016, Lyon, France. pp.201-208, ⟨10.1109/MCSoC.2016.20⟩
Communication dans un congrès
lirmm-01418745v1
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Emerging Non-volatile Memory Technologies Exploration Flow for Processor ArchitectureISVLSI 2015 - International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.460-465, ⟨10.1109/ISVLSI.2015.126⟩
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lirmm-01253337v1
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Potential Applications Based on NVM Emerging TechnologiesDATE 2015 - 18th Design, Automation and Test in Europe Conference and Exhibition, Mar 2015, Grenoble, France. pp.1012-1017, ⟨10.7873/DATE.2015.1120⟩
Communication dans un congrès
lirmm-01253332v1
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Adaptive Power monitoring for self-aware embedded systemsNORCAS 2015 - 1st Nordic Circuits and Systems Conference, Oct 2015, Oslo, Norway. ⟨10.1109/NORCHIP.2015.7364364⟩
Communication dans un congrès
lirmm-01257519v1
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Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE ArchitecturesISVLSI: International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.551-556, ⟨10.1109/ISVLSI.2015.28⟩
Communication dans un congrès
lirmm-01255927v1
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Method for dynamic power monitoring on FPGAsFPL: Field Programmable Logic and Applications, Sep 2014, Munich, Germany. ⟨10.1109/FPL.2014.6927457⟩
Communication dans un congrès
hal-01139163v1
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Power efficient Thermally Assisted Switching Magnetic memory based memory systemsReCoSoC: Reconfigurable and Communication-Centric Systems-on-Chip, May 2014, Montpellier, France. ⟨10.1109/ReCoSoC.2014.6861357⟩
Communication dans un congrès
lirmm-01253331v1
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Trends on the Application of Emerging Nonvolatile Memory to Processors and Programmable DeviceISCAS: International Symposium on Circuits and Systems, May 2013, Beijing, China. pp.101-104, ⟨10.1109/ISCAS.2013.6571792⟩
Communication dans un congrès
lirmm-00813631v1
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Evaluation of hybrid MRAM/CMOS cells for reconfigurable computingNEWCAS: New Circuits and Systems, Jun 2013, Paris, France. ⟨10.1109/NEWCAS.2013.6573676⟩
Communication dans un congrès
lirmm-00818766v1
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Embedded memory hierarchy exploration based on magnetic RAMFTFC: Faible Tension Faible Consommation, Jun 2013, Paris, France. ⟨10.1109/FTFC.2013.6577780⟩
Communication dans un congrès
lirmm-01419132v1
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Modular Framework for Multi-level Multi-device MPSoC Simulation2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum, May 2011, Canada. pp.6, ⟨10.1109/IPDPS.2011.134⟩
Communication dans un congrès
lirmm-00820125v1
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Evaluation of a distributed fault handler method for MPSoCISCAS: International Symposium on Circuits and Systems, May 2011, Rio de Janeiro, Brazil. pp.2329-2332, ⟨10.1109/ISCAS.2011.5938069⟩
Communication dans un congrès
lirmm-00818755v1
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Predictive Dynamic Frequency Scaling for Multi-Processor Systems-on-ChipISCAS'2011: International Symposium on Circuits and Systems, 2011, Rio De Janeiro, RJ, Brazil. pp.1500-1503
Communication dans un congrès
lirmm-00818751v1
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Design of MRAM Based Logic Circuits and its ApplicationsGLSVLSI'11: Great Lakes Symposium on VLSI, Switzerland. pp.431-436
Communication dans un congrès
lirmm-00592491v1
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Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space ExplorationReConFig 2011 - International Conference on Reconfigurable Computing and FPGAs, Nov 2011, Cancun, Mexico. pp.357-362, ⟨10.1109/ReConFig.2011.66⟩
Communication dans un congrès
hal-01139181v1
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High Performance SoC Design Using Magnetic Logic and MemoryVLSI-SoC: Very Large Scale Integration - System-on-Chip, Oct 2011, Hong Kong, China. pp.10-33, ⟨10.1007/978-3-642-32770-4_2⟩
Communication dans un congrès
hal-01519767v1
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An In-Memory Monitoring Database For Self Adaptive MP²SoCsDASIP: Design and Architectures for Signal and Image Processing, Oct 2010, Edimbourg, United Kingdom. pp.97-104, ⟨10.1109/DASIP.2010.5706252⟩
Communication dans un congrès
lirmm-00548822v1
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A Cost-Effective Solution to Increase System Reliability and Maintain Global Performance under Unreliable Silicon in MPSoCReConFig'10: International Conference on ReConFigurable Computing and FPGAs, Cancun, Mexico. pp.346-351
Communication dans un congrès
lirmm-00548835v1
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D-Scale: A Scalable System-Level Dependable Method for MPSoCsATS: Asian Test Symposium, 2010, Shanghai, China. pp.198-205
Communication dans un congrès
lirmm-00545123v1
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Flexible and Distributed Real-Time Control on a 4G Telecom MPSoCISCAS'10: IEEE International Symposium on Circuits and Systems, Paris, France. pp.3961-3964
Communication dans un congrès
lirmm-00498529v1
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A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined RadioISVLSI'10: IEEE Computer Society Annual Symposium on VLSI, Lixouri, Cephalonia, Greece. pp.345-350
Communication dans un congrès
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Heterogeneous vs Homogeneous MPSoC Approaches for a Mobile LTE ModemDATE 2010 - Design, Automation and Test in Europe, Mar 2010, Dresden, Germany. pp.184-189
Communication dans un congrès
lirmm-00436680v1
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Exploration of Virtualization Techniques for Achieving Adaptability in Heterogeneous MPSoCsColloque GDR SoC-SiP, 2010, Paris, France
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lirmm-00548797v1
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Evaluating the Impact of Task Migration in Multi-Processor Systems-on-ChipSBCCI 2010 - 23rd Symposium on Integrated Circuits and Systems Design, Sep 2010, Sao Paulo, Brazil. pp.73-78, ⟨10.1145/1854153.1854174⟩
Communication dans un congrès
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Survey of New Trends in Industry for Programmable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Innovation in FPGAs2010 International Conference on Field Programmable Logic and Applications; FPL2010, Aug 2010, Milan, Italy. pp.291-297, ⟨10.1109/FPL.2010.66⟩
Communication dans un congrès
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Providing Better Multi-Processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback MechanismReConFig 2010 - International Conference on ReConFigurable Computing and FPGAs, Dec 2010, Cancun, Mexico. pp.382-387, ⟨10.1109/ReConFig.2010.17⟩
Communication dans un congrès
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Exploration of Task Migration Policies on the HS-Scale SystemReCoSoc'08: 4th International Workshop on Reconfigurable Communication Centric System-On-Chips, Barcelona, Spain. pp.48-54
Communication dans un congrès
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Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoCReConFig'08: International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico, pp.235-240
Communication dans un congrès
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eFPGA Architecture Explorations: CAD & Silicon Analysis of Beyond 90nm Technologies to Investigate New Dimensions of Future InnovationsReCoSoc'08: 4th International Workshop on Reconfigurable Communication-Centric SoCs, Barcelona, Spain. pp.17-24
Communication dans un congrès
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Power Consumption Reduction Explorations in Processors by Enhancing Performance using Small ESL Reprogrammable eFPGAsReConFig'08: International Conference on Reconfigurable Computing and FPGA's, Cancun, Mexico, pp.313-318
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Dynamic and Distributed Frequency Assignment for Energy and Latency Constrained MP-SoCDATE 2009 - 12th Design, Automation and Test in Europe Conference and Exhibition, Apr 2009, Nice, France. pp.1564-1567, ⟨10.1109/DATE.2009.5090912⟩
Communication dans un congrès
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MRAM based eFPGAs: programming and silicon flows, exploration environments, MRAM current state in Industry and its unique potentials for FPGAsReConFig'09: International Conference on ReConFigurable Computing and FPGAs, Dec 2009, Cancun, Mexico, pp.6
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Exploration of Power Reduction and Performance Enhancement in LEON3 Processor with ESL Reprogrammable e-FPGA In Processor Pipeline and as a Co-processorDATE 2009 - 12th Design, Automation and Test in Europe Conference and Exhibition, Apr 2009, Nice, France. pp.184-189, ⟨10.1109/DATE.2009.5090655⟩
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Baf: A Bio-Inspired Agent Framework for Distributed Pervasive ApplicationsGEM'08: Genetic and Evolutionary Mechanisms, Las Vegas, USA, pp.N/A
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A Non-Volatile Run-Time FPGA using Thermally Assisted Switching MRAMSFPL'08: IEEE International Conference on Field Programmable Logic and Applications, Heidelberg, Allemagne, pp.421-426
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Hierarchical Code Correction and Reliability Management in Embedded NOR Flash MemoriesETS: European Test Symposium, May 2008, Verbania, Italy. pp.84-90
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Convergence Analysis of Run-Time Distributed Optimization on Adaptive Systems Using Game TheoryFPL'08: International Conference on Field Programmable Logic and Applications, Sep 2008, Heidelberg, Germany. pp.555-558, ⟨10.1109/FPL.2008.4630007⟩
Communication dans un congrès
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Bio-Inspiration Helps Computers: An New MachineFPL'08: The 18th International Conference on Field-Programmable Logic and Applications, Sep 2008, Heidelberg, Germany. pp.697-698
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A Non-Volatile Field Programmable Gate Array using Thermally Assisted Switching MRAMsICESCA'08: International Conference on Embedded Systems & Critical Applications, May 2008, Gammarth, Tunisia. pp.95-100
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MPI-Based Adaptive Task Migration Support on the HS-Scale SystemISVLSI 2008 - IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France. pp.105-110, ⟨10.1109/ISVLSI.2008.87⟩
Communication dans un congrès
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Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game TheoryISVLSI'08: IEEE Computer Society Annual Symposium on VLSI, Apr 2008, Montpellier, France, pp.375-380
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A Code Compression Method with Encryption and Integrity CheckingCryptArchi: Cryptographic Architectures, Jun 2007, Montpellier, France
Communication dans un congrès
lirmm-00179964v1
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Technological Hybridization for Efficient Runtime Reconfigurable FPGAsISVLSI'07: IEEE Computer Society Annual Symposium on VLSI, May 2007, Porto Allegre, Brazil, pp.29-34
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Evaluation of Design for Reliability Techniques in Embedded Flash MemoriesDATE: Design, Automation and Test in Europe, Apr 2007, Nice, France. pp.1593-1598, ⟨10.1109/DATE.2007.364529⟩
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The Perplexus ProjectDASIP'07: Workshop on Design and Architectures for Signal and Image Processing, Nov 2007, Grenoble, France, France. pp.N/A
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Architecture for Highly Reliable Embedded Flash MemoriesDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2007, Krakow, Poland. pp.75-80, ⟨10.1109/DDECS.2007.4295257⟩
Communication dans un congrès
lirmm-00161636v1
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An Adaptative MP-SoC Architecture for Embedded SystemsCAR'07: 2nd National Workshop on Control Architectures of Robots: From Models to Execution on Distributed Control Architectures, Jun 2007, Paris, France. pp.101-107
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lirmm-00179505v1
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HS-Scale: A Hardware-Software Scalable MP-SOC Architecture for Embedded SystemsISVLSI'07: IEEE Computer Society Annual Symposium on VLSI, 2007, Porto Allegre, Brazil, pp.21-28
Communication dans un congrès
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HS Scale: A Run-Time Adaptable MP-SoC ArchitectureReCoSoC'07: International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2007, Montpellier, France. pp.CDROM
Communication dans un congrès
lirmm-00179482v1
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IBC-EI: An Instruction Based Compression Method with Encryption and Integrity CheckingReCoSoC'07: International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2007, Montpellier, France. pp.138-145
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lirmm-00179500v1
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TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay AttacksCHES'07: Workshop on Cryptographic Hardware and Embedded Systems, Sep 2007, Vienna, Austria, pp.289-302, ⟨10.1007/978-3-540-74735-2_20⟩
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lirmm-00179776v1
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Application Case Studies on HS-Scale, a MP-SOC for Embbeded SystemsEmbedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Jul 2007, Samos, Greece. pp.88-95, ⟨10.1109/ICSAMOS.2007.4285738⟩
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How to Add the Integrity Checking Capability to Block Encryption AlgorithmsPRIME'06, Jun 2006, France. pp.369-372
Communication dans un congrès
emse-00493940v1
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Remanent SRAM Structure for Runtime Reconfigurable FPGAReCoSoC'06: Second Reconfigurable Communication-Centric Systems-on-Chip Workshop, Jul 2006, Montpellier, France. pp.124-130
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Conception d'un FPGA Reconfigurable Dynamiquement à la Mémoire de Reconfiguration Non Volatile MagnétiqueJNRDM: Journées Nationales du Réseau Doctoral de Microélectronique, May 2006, Rennes, France
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Implémentation Matérielle d'une Arithmétique Résistante aux FuitesRenPar/ SympAAA/ CFSE - Rencontres Francophones en Parallélisme, Architecture, Adéquation Algorithmes Architecture et Système, Oct 2006, Canet en Roussillon, France. pp.57-74
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How to Secure Embedded Programmable Gate Arrays?ReCoSoC 2006 - 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Jul 2006, Montpellier, France. pp.52-59
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Securing Embedded Programmable Gate Arrays in Secure CircuitsIPDP 2006 - 20th IEEE International Parallel & Distributed Processing Symposium, Apr 2006, Rhodes Island, Greece. pp.215-221, ⟨10.1109/IPDPS.2006.1639483⟩
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lirmm-00102781v1
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New Non-Volatile FPGA Concept Using Magnetic Tunneling JunctionISVLSI'06: IEEE Computer Society Annual Symposium on VLSI, Mar 2006, Karlsruhe (Germany), pp.269-274
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Efficient Combination of data Encryption and Integrity Checking for Embedded SystemsReCoSoC'06: Second Reconfigurable Communication-Centric Systems-on-Chip Workshop, Jul 2006, Montpellier, France. pp.68-75
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A Leak Resistant Architecture Against Side Channel AttacksFPL: Field-Programmable Logic and Applications, Aug 2006, Madrid, Spain. pp.881-884, ⟨10.1109/FPL.2006.311335⟩
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Dynamic hardware multiplexing: improving adaptability with a run time reconfiguration managerISVLSI 2006 - IEEE Computer Society Annual Symposium on VLSI, Mar 2006, Karlsruhe, Germany. pp.251-256, ⟨10.1109/ISVLSI.2006.38⟩
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Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the aPACHES' PlatformARC: Applied Reconfigurable Computing, Mar 2006, Delft, Netherlands. pp.134-145, ⟨10.1007/11802839_19⟩
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Magnetic Tunnelling Junction Based FPGAFPGA 2006 - ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, Feb 2006, Monterey, CA, United States. pp.123-130, ⟨10.1145/1117201.1117220⟩
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lirmm-00102779v1
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A Contextual Resources Use: A Proof of Concept Through the APACHES'PlatormDDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2006, Prague, Czech Republic. pp.44-49, ⟨10.1109/DDECS.2006.1649568⟩
Communication dans un congrès
lirmm-00102754v1
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PE-ICE: Parallelized Encryption and Integrity Checking EngineDDECS'06: 9th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr 2006, Prague, Czech Republic. pp.143-144
Communication dans un congrès
lirmm-00102755v1
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A Leak Resistant SoC to Counteract Side Channel AttacksSOC'06: International Symposium on System-On-Chip, Nov 2006, Tampere, Finlande, pp.N/A
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lirmm-00352713v1
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A Parallelized Way to Provide Data Encryption and Integrity Checking on a Processor-Memory BusDAC: Design Automation Conference, Jul 2006, San Francisco, CA, United States
Communication dans un congrès
lirmm-00102783v1
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How to Add the Integrity Checking Capability to Block Encryption AgorithmsIEEE PRIME'06: Ph.D. Research in MicroElectronics and Electronics, Jun 2006, Otranto, Lecce, Italy. pp.369-372
Communication dans un congrès
lirmm-00102846v1
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Current Mask Generation: A Transistor Level Security Against DPA AttacksSBCCI 2005 - 18th annual symposium on Integrated circuits and system design, Sep 2005, Florianolpolis, Brazil. pp.115-120, ⟨10.1145/1081081.1081114⟩
Communication dans un congrès
lirmm-03704230v1
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A New Hardware Counter Measure for Masking Power Signatures of CryptocoresRECoSoC'05: 1st International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2005, Montpellier, France. pp.169-176
Communication dans un congrès
lirmm-00355889v1
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Gestion Matérielle du Parallélisme pour les Architectures Reconfigurables à Grain EpaisJFAAA'05: Journées Francophones sur l'Adéquation Algorithme Architecture, Jan 2005, Dijon, France. pp.15-20
Communication dans un congrès
lirmm-00106510v1
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Hardware Engines for Bus Encryption: a Survey of Existing TechniquesDATE 2005 - 8th Design, Automation and Test in Europe Conference and Exhibition, Mar 2005, Munich, Germany. pp.40-45, ⟨10.1109/DATE.2005.170⟩
Communication dans un congrès
lirmm-00106453v1
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Intégration d'un Coeur Reconfigurable dans un Composant SécuriséJNRDM 2005 - 8e Journées Nationales du Réseau Doctoral de Microélectronique, May 2005, Paris, France. pp.464-465
Communication dans un congrès
lirmm-00106531v1
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A RTR Hardware Controller for DSP Kernel Scheduling in Coarse Grain Reconfigurable ArchitectureIPDPS'05: International Parallel and Distributed Processing SymposiumRAW'05: Reconfigurable Architectures Workshop, Apr 2005, pp.485-489
Communication dans un congrès
lirmm-00105958v1
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A Mesh Based Network on Chip characterization : A GALS ApproachDCIS 2005 - 20th Conference on Design of Circuits and Integrated Systems, Nov 2005, Lisbonne, Portugal. pp.10-15
Communication dans un congrès
lirmm-00106054v1
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Current Mask Generation: A hardware Countermeasure Against DPA AttacksSBCCI'05: 18th Symposium on Integrated Circuits and Systems Design, Sep 2005
Communication dans un congrès
lirmm-00106053v1
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Automatic Task Scheduling/Loop Unrolling Using Dedicated RTR Controllers in Coarse Grain Recongigurable ArchitecturesIPDPS'05: International Parallel and Distributed Processing Symposium, RAW'05: Reconfigurable Architectures Workshop, Apr 2005, Denver, Colorado (USA), pp.148
Communication dans un congrès
lirmm-00105985v1
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Packet-Switching Network-On-Chip Features Exploration and CharacterizationVLSI-SOC'05: IFIP International Conference on Very Large Scale Integration, Oct 2005, Perth, Australia. pp.403-409
Communication dans un congrès
lirmm-00106440v1
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Non-Volatile SRAM-FPGA based on Magnetic Tunnelling JunctionRECoSoC'05: 1st International Workshop on Reconfigurable Communication Centric System-On-Chips, Jun 2005, Montpellier, France. pp.113-120
Communication dans un congrès
lirmm-00355885v1
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Current Mask Generation: an Analog Circuit to Thwart DPA AttacksVLSI-SoC 2005 - 13th International Conference on Very Large Scale Integration of System on Chip, Oct 2005, Perth, Australia. pp.317-330, ⟨10.1007/978-0-387-73661-7_20⟩
Communication dans un congrès
lirmm-00102782v1
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Run-Time Scheduling for Random Multi Tasking in Reconfigurable CoprocessorsFPL'05 IEEE : 15th International Workshop on Field-Programmable Logic and Applications, Aug 2005, Tampere (Finlande), pp.703-706
Communication dans un congrès
lirmm-00106057v1
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Magnetic remanent memory structures for dynamically reconfigurable FPGAFPL 2005 - 14th International Conference on Field Programmable Logic and Applications, Aug 2005, Tampere, Finland. pp.687-690, ⟨10.1109/FPL.2005.1515813⟩
Communication dans un congrès
lirmm-00106055v1
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A GALS Network on Chip with Quality of Service supportSAME'05: Sophia-Antipolis Forum on MicroElectronics, Oct 2005, Sophia Antipolis, France. pp.199-207
Communication dans un congrès
lirmm-00106526v1
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Réseaux d'interconnexion pour les systèmes sur Puce : le réseau HERMESSCS 2004 - Signaux, Circuits et Systèmes, Mar 2004, Monastir, Tunisia. pp.35-40
Communication dans un congrès
lirmm-00352701v1
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Metrics for Digital Signal Processing Architectures Characterization: Remanence and ScalabilitySAMOS 2004 - 4th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Jul 2004, Samos, Greece. pp.128-137
Communication dans un congrès
lirmm-00269656v1
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Réseau d'interconnexion pour les systèmes sur pucesJNRDM'04: 7èmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2004, Marseille, France. pp.451-453
Communication dans un congrès
lirmm-00355900v1
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System On Chip (SOC) : Du Composant... au ComposantJournées Nationales du GDR et RTP Nanoélectronique, May 2004, Aussois, France
Communication dans un congrès
lirmm-00108673v1
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A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring.FPL 2003 - 12th International Workshop on Field-Programmable Logic and Applications, Sep 2003, Lisbon, Portugal. pp.722-732, ⟨10.1007/978-3-540-45234-8_70⟩
Communication dans un congrès
lirmm-00269558v1
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Comparaison des Architectures Dédiées au Traitement des Données NumériquesJNRDM'03 : 6ièmes Journées Nationales du Réseau Doctoral de Microélectronique, May 2003, Toulouse (France), France. pp.115-117
Communication dans un congrès
lirmm-00269542v1
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Are Coarse Grain Reconfigurable Architectures Suitable for Cryptography?12th International Conference on Very Large Scale Integration of System-on-Chip (VLSI-SoC), Dec 2003, Darmstadt, Germany. pp.276-281
Communication dans un congrès
lirmm-00269699v1
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Comparaison d'Architectures Dédiées au Traitement Numériques des Données : du Processeur aux Architectures ReconfigurablesRenPar/ SympAAA/ CFSE - Rencontres Francophones en Parallélisme, Architecture, Adéquation Algorithmes Architecture et Système, Oct 2003, La Colle sur Loup, France. pp.322-326
Communication dans un congrès
lirmm-00269654v1
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Metrics for Reconfigurable Architectures Characterization: Remanence and ScalabilityIPDPS: International Parallel and Distributed Processing Symposium, Apr 2003, Nice, France. pp.176-180, ⟨10.1109/IPDPS.2003.1213324⟩
Communication dans un congrès
lirmm-00269655v1
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Caractérisation et Comparaison d'Architectures Reconfigurables Dynamiquement, un exemple : Le Systolic RingJFAAA'02: Journées Francophones sur l'Adéquation Algorithme Architecture, Dec 2002, Monastir, Tunisie. pp.30-34
Communication dans un congrès
lirmm-00269344v1
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Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP ApplicationDATE: Design, Automation and Test in Europe, Mar 2002, Paris, France. pp.553-566, ⟨10.1109/DATE.2002.998355⟩
Communication dans un congrès
lirmm-00268531v1
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Architectures Reconfigurables Dynamiquement pour Applications TSIColloque du GDR CAO de Circuits et Systèmes Intégrés, May 2002, Paris, France. pp.67-70
Communication dans un congrès
lirmm-00269321v1
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Exploration of Magnetic RAM Based Memory Hierarchy for Multicore ArchitectureISVLSI: International Symposium on Very Large Scale Integration, Jul 2014, Tampa, FL, United States. pp.248-251, 2014, ⟨10.1109/ISVLSI.2014.29⟩
Poster de conférence
lirmm-01253350v1
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Self-adaptability in Multi-processor Embedded SystemsColloque GDR SoC-SiP, Jun 2009, Paris, France. 2009
Poster de conférence
lirmm-00406761v1
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Distributed Pervasive Phylogenetic Application using a Bio-Inspired Agent FrameworkColloque GDR SoC-SiP, 2008, Paris, France. 2008
Poster de conférence
lirmm-00406765v1
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Towards Self-Adaptability a Scalable MP-SOC Architecture ApproachColloque du GDR SoC-SiP, 2007, Paris, France. 2007
Poster de conférence
lirmm-00406773v1
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Emerging Non-Volatile Technologies for Runtime FPGA Configuration MemoryFPGA'07: Fifteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, ACM, pp.227, 2007
Poster de conférence
lirmm-00138834v1
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Perplexus ProjectColloque du GDR SoC-SiP, 2007, Paris, France. 2007
Poster de conférence
lirmm-00406772v1
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Embedded Programmable Devices Using Magnetic RAM CellsEUSPEN: European Society for Precision Engineering and Nanotechnology, May 2005, Montpellier, France. 5th International Conference of the European Society for Precision Engineering and Nanotechnology, pp.337-340, 2005
Poster de conférence
lirmm-00106000v1
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A Parallel Architecture for Software and Hardware ExplorationRECoSoC: Reconfigurable Communication Centric System-On-Chips, Jun 2005, Montpellier, France. 2005
Poster de conférence
lirmm-00355891v1
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Packet-Switching Network-On-Chip Feature Exploration and CharacterizationRECoSoC'05: Reconfigurable Communication-Centric SoCs, Jun 2005, Montpellier, France. 2005
Poster de conférence
lirmm-00355893v1
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Dynamic Hardware Multiplexing for Coarse Grain Reconfigurable ArchitecturesFPGA'05: ACM/SIGDA 9th International Symposium on Field Programmable Gate Arrays, Feb 2005, Monterey, CA, United States. ACM Press, 2005
Poster de conférence
lirmm-00105959v1
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The Systolic Ring: A Scalable Dynamically Reconfigurable Core for Embedded SystemsSAME'02: Sophia-Antipolis Forum on MicroElectronics, Oct 2002, Sophia-Antipolis, France. pp.85-90, 2002
Poster de conférence
lirmm-00269322v1
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Towards Autonomous Scalable Integrated SystemsDesign Technology for Heterogeneous Embedded Systems, Springer, pp.63-89, 2012, 978-94-007-1124-2. ⟨10.1007/978-94-007-1125-9_4⟩
Chapitre d'ouvrage
lirmm-01399454v1
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Embedded Systems Security for FPGASecurity Trends for FPGAS
Chapitre d'ouvrage
lirmm-00818934v1
From Secured to Secure Reconfigurable Systems, pp.137-187, 2011, 978-94-007-1337-6. ⟨10.1007/978-94-007-1338-3_6⟩ |
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Countermeasures Against Physical Attacks in FPGAsSecurity Trends for FPGAS
Chapitre d'ouvrage
lirmm-00809330v1
From Secured to Secure Reconfigurable Systems, Springer, pp.73-100, 2011, 978-94-007-1337-6. ⟨10.1007/978-94-007-1338-3_4⟩ |
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An Introduction to Multi-Core System on Chip - Trends and ChallengesHübner, Michael; Becker, Jürgen. Multiprocessor System-on-Chip - Hardware Design and Tool Integration, Springer, pp.1-21, 2011, Chapter 1, 978-1-4419-6459-5. ⟨10.1007/978-1-4419-6460-1_1⟩
Chapitre d'ouvrage
lirmm-00574947v1
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Current Mask Generation: An Analog Circuit to Thwart DPA AttacksVLSI-SoC: From Systems to Silicon, Springer, pp.317-330, 2007, 978-0-387-73660-0
Chapitre d'ouvrage
lirmm-00203662v1
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A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory BusNadine Azémard, Philippe Maurine, Johan Vounckx. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 4148/2006, Springer Berlin / Heidelberg, pp.267-279, 2006, Lecture Notes in Computer Science, 978-3-540-39094-7. ⟨10.1007/11847083_44⟩
Chapitre d'ouvrage
lirmm-00109765v1
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Dynamically Reconfigurable Architectures for Digital Signal Processing ApplicationsSOC Design Methodologies, 90, Kluwer Academic Publishers 2002, pp.63-74, 2002, IFIP — The International Federation for Information Processing, 978-1-4757-6530-4. ⟨10.1007/978-0-387-35597-9_6⟩
Chapitre d'ouvrage
lirmm-00108929v1
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Cellule de mémoire Non-VolatileFrance, N° de brevet: F644/249FR. 2009, pp.20
Brevet
lirmm-00411387v1
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Architecture de Calcul Logique comprenant plusieurs Modes de ConfigurationÉtats-Unis, N° de brevet: 0204161. 9763. 2002, pp.P/N
Brevet
lirmm-00268653v1
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Architecture de Transport de Données en Anneau comprenant un Réseau de RétropopagationÉtats-Unis, N° de brevet: 0204162. 9764. 2002, pp.P/N
Brevet
lirmm-00268654v1
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Performance and Energy Impact of Enhanced Cache Replacement Policy on STT-MRAM LLC2021
Pré-publication, Document de travail
lirmm-03341604v1
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Emerging NVM Technologies in Main Memory for Energy-Efficient HPC: an Empirical Study2019
Pré-publication, Document de travail
lirmm-02135043v1
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Deliverable D3.2 - Evaluation of selected memory and communication technologies and exploitation opportunities in compilation and runtime management[Research Report] LIRMM (UM, CNRS); Inria Rennes – Bretagne Atlantique. 2017
Rapport
lirmm-03168318v1
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Deliverable D3.1 – Novel memory and communication technologies[Research Report] LIRMM (UM, CNRS). 2016
Rapport
lirmm-03168312v1
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