Gilles Sassatelli
16
Documents
Identifiants chercheurs
- gilles-sassatelli
- 0000-0002-6396-286X
- IdRef : 069998035
Présentation
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Normally-Off Computing and Checkpoint/Rollback for Fast, Low-Power, and Reliable DevicesIEEE Magnetics Letters, 2017, 8, pp.1-5. ⟨10.1109/LMAG.2017.2712780⟩
Article dans une revue
hal-01767897v1
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Non-Volatile Processor Based on MRAM for Ultra-Low-Power IoT DevicesACM Journal on Emerging Technologies in Computing Systems, 2017, 13 (2), pp.1-23. ⟨10.1145/3001936⟩
Article dans une revue
lirmm-01419425v1
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Exploring MRAM Technologies for Energy Efficient Systems-On-ChipIEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2016, 6 (3), pp.279-292. ⟨10.1109/JETCAS.2016.2547680⟩
Article dans une revue
lirmm-01419429v1
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Embedded Memory Hierarchy Exploration Based on Magnetic Random Access MemoryJournal of Low Power Electronics and Applications, 2014, 4 (3), pp.214-230. ⟨10.3390/jlpea4030214⟩
Article dans une revue
lirmm-01306304v1
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Using multifunctional standardized stack as universal spintronic technology for IoTDATE 2018 - 21st Design, Automation and Test in Europe Conference and Exhibition, Mar 2018, Dresden, Germany. pp.931-936, ⟨10.23919/DATE.2018.8342143⟩
Communication dans un congrès
hal-01864468v1
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Embedded systems to high performance computing using STT-MRAMDATE 2017 - 20th Design, Automation and Test in Europe Conference and Exhibition, Mar 2017, Lausanne, Switzerland. pp.536-541, ⟨10.23919/DATE.2017.7927046⟩
Communication dans un congrès
lirmm-01548996v1
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MAGPIE: System-level Evaluation of Manycore Systems with Emerging Memory TechnologiesEMS: Emerging Memory Solutions, Mar 2017, Lausanne, Switzerland
Communication dans un congrès
lirmm-01467328v1
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Flot automatique d’évaluation pour l’exploration d’architectures à base de mémoires non volatilesComPAS: Conférence en Parallélisme, Architecture et Système, Jul 2016, Lorient, France
Communication dans un congrès
lirmm-01345975v1
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Loop Optimization in Presence of STT-MRAM Caches: a Study of Performance-Energy TradeoffsPATMOS: Power and Timing Modeling, Optimization and Simulation, Sep 2016, Bremen, Germany. pp.162-169, ⟨10.1109/PATMOS.2016.7833682⟩
Communication dans un congrès
hal-01347354v1
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Emerging Non-volatile Memory Technologies Exploration Flow for Processor ArchitectureISVLSI 2015 - International Symposium on Very Large Scale Integration, Jul 2015, Montpellier, France. pp.460-465, ⟨10.1109/ISVLSI.2015.126⟩
Communication dans un congrès
lirmm-01253337v1
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Potential Applications Based on NVM Emerging TechnologiesDATE 2015 - 18th Design, Automation and Test in Europe Conference and Exhibition, Mar 2015, Grenoble, France. pp.1012-1017, ⟨10.7873/DATE.2015.1120⟩
Communication dans un congrès
lirmm-01253332v1
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Power efficient Thermally Assisted Switching Magnetic memory based memory systemsReCoSoC: Reconfigurable and Communication-Centric Systems-on-Chip, May 2014, Montpellier, France. ⟨10.1109/ReCoSoC.2014.6861357⟩
Communication dans un congrès
lirmm-01253331v1
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Embedded memory hierarchy exploration based on magnetic RAMFTFC: Faible Tension Faible Consommation, Jun 2013, Paris, France. ⟨10.1109/FTFC.2013.6577780⟩
Communication dans un congrès
lirmm-01419132v1
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Exploration of Magnetic RAM Based Memory Hierarchy for Multicore ArchitectureISVLSI: International Symposium on Very Large Scale Integration, Jul 2014, Tampa, FL, United States. pp.248-251, 2014, ⟨10.1109/ISVLSI.2014.29⟩
Poster de conférence
lirmm-01253350v1
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Deliverable D3.2 - Evaluation of selected memory and communication technologies and exploitation opportunities in compilation and runtime management[Research Report] LIRMM (UM, CNRS); Inria Rennes – Bretagne Atlantique. 2017
Rapport
lirmm-03168318v1
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Deliverable D3.1 – Novel memory and communication technologies[Research Report] LIRMM (UM, CNRS). 2016
Rapport
lirmm-03168312v1
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