Gilles Sassatelli
9
Documents
Identifiants chercheurs
- gilles-sassatelli
- 0000-0002-6396-286X
- IdRef : 069998035
Présentation
Publications
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Block- Level Added Redundancy Explicit Authentication for Parallelized Encryption and Integrity Checking of Processor- Memory TransactionsLecture Notes in Computer Science, 2010, 6340/2010, pp.231-260. ⟨10.1007/978-3-642-17499-5_10⟩
Article dans une revue
lirmm-00594999v1
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TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay AttacksCHES'07: Workshop on Cryptographic Hardware and Embedded Systems, Sep 2007, Vienna, Austria, pp.289-302, ⟨10.1007/978-3-540-74735-2_20⟩
Communication dans un congrès
lirmm-00179776v1
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Efficient Combination of data Encryption and Integrity Checking for Embedded SystemsReCoSoC'06: Second Reconfigurable Communication-Centric Systems-on-Chip Workshop, Jul 2006, Montpellier, France. pp.68-75
Communication dans un congrès
lirmm-00353366v1
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A Parallelized Way to Provide Data Encryption and Integrity Checking on a Processor-Memory BusDAC: Design Automation Conference, Jul 2006, San Francisco, CA, United States
Communication dans un congrès
lirmm-00102783v1
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How to Add the Integrity Checking Capability to Block Encryption AgorithmsIEEE PRIME'06: Ph.D. Research in MicroElectronics and Electronics, Jun 2006, Otranto, Lecce, Italy. pp.369-372
Communication dans un congrès
lirmm-00102846v1
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How to Add the Integrity Checking Capability to Block Encryption AlgorithmsPRIME'06, Jun 2006, France. pp.369-372
Communication dans un congrès
emse-00493940v1
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PE-ICE: Parallelized Encryption and Integrity Checking EngineDDECS'06: 9th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems, Apr 2006, Prague, Czech Republic. pp.143-144
Communication dans un congrès
lirmm-00102755v1
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Hardware Engines for Bus Encryption: a Survey of Existing TechniquesDATE 2005 - 8th Design, Automation and Test in Europe Conference and Exhibition, Mar 2005, Munich, Germany. pp.40-45, ⟨10.1109/DATE.2005.170⟩
Communication dans un congrès
lirmm-00106453v1
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A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory BusNadine Azémard, Philippe Maurine, Johan Vounckx. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 4148/2006, Springer Berlin / Heidelberg, pp.267-279, 2006, Lecture Notes in Computer Science, 978-3-540-39094-7. ⟨10.1007/11847083_44⟩
Chapitre d'ouvrage
lirmm-00109765v1
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