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229 résultats
Formal Analysis of Single Wait VHDL processes for Semantic Based Synthesis12th IEEE International Conference on VLSI Design, Jan 1999, Goa, India. pp.151-156, ⟨10.1109/ICVD.1999.745140⟩
Communication dans un congrès
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A Toolbox to Map System Level Communications on HW/SW Architectures12th International Workshop on Rapid System Prototyping, Jun 2001, Monterey, CA, United States. pp.77-82, ⟨10.1109/IWRSP.2001.933842⟩
Communication dans un congrès
hal-01571013v1
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Modular on chip multi processor for routing applicationsEuro-Par 2004 - 10th European Conference on Parallel computing, Aug 2004, Pise, Italy. pp.847-855, ⟨10.1007/978-3-540-27866-5_113⟩
Communication dans un congrès
istex
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Disydent : un environnement pour la conception de systèmes numériques synchronesSCS congrès international de Signaux Circuits et Systèmes, Mar 2004, Monastir, Tunisie. pp.72-77
Communication dans un congrès
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Teaching basic computer architecture, assembly language programming, and operating system design using RISC-VRISC V week 2019, Oct 2019, Paris, France
Communication dans un congrès
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Multiprocessor System-on-Chip Prototyping Using Dynamic Binary TranslationHandbook of Hardware/Software Codesign, springer, pp.565-591, 2017, 978-94-017-7266-2. ⟨10.1007/978-94-017-7267-9⟩
Chapitre d'ouvrage
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Message-Oriented Devices on FPGAsInternational Symposium on Rapid System Prototyping (RSP 2018), Oct 2018, Torino, Italy. pp.8-14
Communication dans un congrès
hal-02114435v1
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Dynamic Binary Translation of VLIW Codes on Scalar ArchitecturesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 36 (5), pp.789-800. ⟨10.1109/TCAD.2016.2604294⟩
Article dans une revue
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Scalable High-Performance Architecture for Convolutional Ternary Neural Networks on FPGAField Programmable Logic and Applications (FPL), 2017 27th International Conference on, Sep 2017, Gent, Belgium
Communication dans un congrès
hal-01563763v1
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Effective System Level Simulation Techniques and Cross-Layer Perspectives on Low Power DesignDesign, Automation and Test in Europe (DATE'2018), Mar 2018, Dresden, Germany
Communication dans un congrès
hal-01922354v1
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Deterministic reversible MPSoC debugger based on virtual platform execution tracesDesign Automation for Embedded Systems, 2016, 20 (1), pp.47-63. ⟨10.1007/s10617-015-9167-8⟩
Article dans une revue
hal-01332728v1
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Fast Memory Consistency Analysis using Non-Intrusive Simulation TracesThe 2011 System, Software, SoC and Silicon Debug Conference (S4D), Sep 2011, Munich, Germany. pp.17-22
Communication dans un congrès
hal-00671512v1
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3D Integration for NoC-based SoC ArchitecturesSpringer, pp.278, 2011, ⟨10.1007/978-1-4419-7618-5⟩
Ouvrages
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Spidergon STNoC design flowIEEE/ACM International Symposium on Networks on Chip (NoCS'11), May 2011, Pittsburg, Pa., United States. pp.267 - 268
Communication dans un congrès
hal-00680456v1
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Flexible hardware/software interface modeling using high level service based component modelThe 13th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'06), April 3-4, 2006, Nagoya, Japan. pp.85-91
Communication dans un congrès
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On cache coherency and memory consistency issues in NoC based shared memory multiprocessor SoC architectures9th EUROMICRO Conference on Digital System Design (DSD'06), Aug 2006, Dubrovnik, Croatia. pp.53-60, ⟨10.1109/DSD.2006.73⟩
Communication dans un congrès
hal-00143399v1
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Service Dependency Graph for HW/SW Interfaces Modeling: The Motion-JPEG Case Study7th International Conference on ASIC (Asicon'07), Oct 2007, Guilin, China. pp.930-933, ⟨10.1109/ICASIC.2007.4415784⟩
Communication dans un congrès
hal-00222941v1
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Networks-In-Package: Performances management and design methodologyIEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT'08), Apr 2008, Hsinchu, Taiwan. pp.140-143, ⟨10.1109/VDAT.2008.4542432⟩
Communication dans un congrès
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A General Framework for Average-Case Performance Analysis of Shared ResourcesEuromicro Conference on Digital System Design (DSD'13), Sep 2013, Santander, Spain. pp.78-85, ⟨10.1109/DSD.2013.116⟩
Communication dans un congrès
hal-01058906v1
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A system-level overview and comparison of three High-Speed Serial Links: USB 3.0, PCI Express 2.0 and LLI 1.0Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Apr 2013, Karlovy Vary, Czech Republic. pp.147-152
Communication dans un congrès
hal-01058896v1
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A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs12th International Forum on Embedded MPSoC and Multicore, Jul 2012, Quebec, Canada
Communication dans un congrès
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Fast simulation of future 128-bit architecturesDesign, Automation & Test in Europe Conference & Exhibition (DATE 2022), Mar 2022, Anvers (Virtual event), Afghanistan. pp.1131-1134, ⟨10.23919/DATE54114.2022.9774706⟩
Communication dans un congrès
hal-03759696v1
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Fast Cycle Accurate Simulation To Simulate Event-Driven BehaviorICEEC 2004 - International Conference on Electrical Electronic and Computer Engineering, Sep 2004, Cairo, Egypt. pp.37-40, ⟨10.1109/ICEEC.2004.1374374⟩
Communication dans un congrès
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Une gestion efficace des boucles combinatoires pour la simulation au cycle près de systèmes matériel-logicielColloque CAO de Circuits Intégrés et Systèmes GDR 732, May 1999, Aix-en-Provence, France. pp.266-269
Communication dans un congrès
hal-01574791v1
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Lightweight implementation of the POSIX threads API for an On-Chip MIPS multiprocessor with VCI interconnectEmbedded Software for SoC, Springer, pp.25-38, 2003, ⟨10.1007/0-306-48709-8_3⟩
Chapitre d'ouvrage
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Efficient deep learning approach for fault detection in the semiconductor industryADTC 2021 - European Nanoelectronics Applications Design & Technology Conference, Jun 2021, Grenoble, France
Communication dans un congrès
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Low Power Tiny Binary Neural Network with improved accuracy in Human Recognition SystemsEuromicro Conference on Digital System Design (DSD 2020), Aug 2020, Kranj (virtual), Slovenia. pp.309-315, ⟨10.1109/DSD51259.2020.00057⟩
Communication dans un congrès
hal-03106955v1
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Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCsIEEE Transactions on Computers, 2013, 62 (3), pp.609-615. ⟨10.1109/TC.2011.239⟩
Article dans une revue
hal-01138285v1
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Simulation rapide des systèmes multiprocesseursArchitecture, hier, aujourd'hui, demain", Colloque en l'honneur de Michel Auguin, Daniel Etiemble et Bernard Goossens, Jul 2018, Toulouse, France
Communication dans un congrès
hal-02132895v1
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Architecture de communication à base de sérialiseur asynchrone entre circuits déposés sur des substrats de silicium empilésFrance, Patent n° : 09/53637. 2009
Brevet
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