Frédéric Mallet
Professeur des Universités
Université Côte d'Azur
32
Documents
Affiliations actuelles
- 451999
- 13009
- 478607
- 1039632
Identifiants chercheurs
frederic-mallet- ResearcherId : H-3942-2011
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0000-0002-9088-9821
- IdRef : 060764325
- ResearcherId : http://www.researcherid.com/rid/H-3942-2011
Publications
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Logical Time: observation vs. implementationSoftware Engineering Notes, 2011, 36 (1), pp.1--8. ⟨10.1145/1921532.1921554⟩
Article dans une revue
inria-00576647v1
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Un processus automatique pour concevoir les profils UMLRevue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, 2010, 29 (5), pp.391-419
Article dans une revue
inria-00482745v1
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The Clock Constraint Specification Language for building timed causality modelsInnovations in Systems and Software Engineering, 2010, 6 (1-2), pp.99-106. ⟨10.1007/s11334-009-0109-0⟩
Article dans une revue
inria-00464894v1
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Les modèles de temps de MARTE et CCSLGénie logiciel : le magazine de l'ingénierie du logiciel et des systèmes, 2009, 89, pp.44-49
Article dans une revue
inria-00416597v1
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Modèle de contraintes temporelles pour systèmes polychronesJournal Européen des Systèmes Automatisés (JESA), 2009, 7-9 (43), pp.725-739
Article dans une revue
inria-00434462v1
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Logical time @ work: the RT-Simex projectSophia Antipolis Formal Approach, Apr 2011, Sophia, France
Communication dans un congrès
inria-00587151v1
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Polychronous Analysis of Timing Constraints in UML MARTEIEEE International Workshop on Model-Based Engineering for Real-Time Embedded Systems Design, May 2010, Parador of Carmona, Spain. 7 p
Communication dans un congrès
inria-00497249v1
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VHDL Observers for Clock Constraint CheckingSymposium on Industrial Embedded Systems, Jul 2010, trento, Italy. ⟨10.1109/SIES.2010.5551372⟩
Communication dans un congrès
inria-00587107v1
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Marte CCSL to execute East-ADL Timing RequirementsInt. Symp. on Object/component/service-oriented Real-time distributed Computing (ISORC'09), Mar 2009, Tokyo, Japan. pp.249-253, ⟨10.1109/ISORC.2009.18⟩
Communication dans un congrès
inria-00383262v1
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On the semantics of UML/Marte Clock ConstraintsInt. Symp. on Object/component/service-oriented Real-time distributed Computing (ISORC'09), Mar 2009, Tokyo, Japan. pp.301-312, ⟨10.1109/ISORC.2009.27⟩
Communication dans un congrès
inria-00383279v1
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An Automated Process for Implementing Multilevel Domain ModelsSoftware Language Engineering, Oct 2009, Denver, Colorado, United States. pp.314-333, ⟨10.1007/978-3-642-12107-4_22⟩
Communication dans un congrès
inria-00464880v1
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Executing AADL models with UML/MarteInt. Conf. Engineering of Complex Computer Systems - ICECCS'09, Jun 2009, Potsdam, Germany. pp. 371-376, ⟨10.1109/ICECCS.2009.10⟩
Communication dans un congrès
inria-00416592v1
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Specification and Verification of Time Requirements with CCSL and EsterelLanguages, Compilers, and Tools for Embedded Systems, Jun 2009, Dublin, Ireland. pp.167-176, ⟨10.1145/1543136.1542475⟩
Communication dans un congrès
inria-00416654v1
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Time Modeling in MARTEECSI Forum on specification & Design Languages (FDL), ECSI, Sep 2007, Barcelona, Spain. pp.268-273
Communication dans un congrès
inria-00204481v1
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A multiform time approach to real-time system modeling: Application to an automotive systemIEEE Int. Symp. on Industrial Embedded Systems (SIES), Jul 2007, Lisbon, Portugal. pp.234-241, ⟨10.1109/SIES.2007.4297340⟩
Communication dans un congrès
inria-00204508v1
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Modeling Time(s)ACM/IEEE Int. Conf. on Model Driven Engineering Languages and Systems (MoDELS/UML), Oct 2007, Nashville, TN, United States. pp. 559-573, ⟨10.1007/978-3-540-75209-7_38⟩
Communication dans un congrès
inria-00204489v1
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Modeling of Immediate vs. Delayed Data Communications: from AADL to UML MARTEECSI Forum on specification & Design Languages (FDL), ECSI, Sep 2007, Barcelona, Spain. pp.249-254
Communication dans un congrès
inria-00204484v1
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Multiform Time in UML for Real-time Embedded ApplicationsIEEE Int. Conf. on Real-Time Computing Systems and Applications (RTCSA), Aug 2007, Daegu, South Korea. pp.232-237, ⟨10.1109/RTCSA.2007.51⟩
Communication dans un congrès
inria-00204503v1
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From UML to Petri Nets for non functional Property VerificationIEEE International Symposium on Industrial Embedded Systems, 2006. IES '06., Oct 2006, Sophia antipolis, France. ⟨10.1109/IES.2006.357475⟩
Communication dans un congrès
inria-00371277v1
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MARTE: a new OMG profile RFP for the Modeling and Analysis of Real-Time Embedded SystemsDAC 2005 Workshop - UML for SoC Design, Jun 2005, Anaheim California, United States
Communication dans un congrès
hal-02466757v1
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The Time Model of Logical Clocks available in the OMG MARTE profileSandeep K. Shukla and Jean-Pierre Talpin. Synthesis of Embedded Software: Frameworks and Methodologies for Correctness by Construction, Springer Science+Business Media, LLC 2010, pp.28, 2010, 978-1-4419-6399-4
Chapitre d'ouvrage
inria-00495664v1
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Modeling AADL data-communications with UML MARTEEugenio villar. Embedded Systems Specification and Design Languages, 10, Springer, pp.150-170, 2008, Lecture Notes in Electrical Engineering, 978-1-4020-8296-2. ⟨10.1007/978-1-4020-8297-9_11⟩
Chapitre d'ouvrage
inria-00371366v1
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TimeSquareFrance, Patent n° : IDDN.FR.001.430002.000.S.A.2012.000.10600. 2012
Brevet
hal-01355710v1
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