Frédéric Mallet
Professeur des Universités
Université Côte d'Azur
25
Documents
Affiliations actuelles
- 451999
- 13009
- 478607
- 1039632
Identifiants chercheurs
frederic-mallet- ResearcherId : H-3942-2011
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0000-0002-9088-9821
- IdRef : 060764325
- ResearcherId : http://www.researcherid.com/rid/H-3942-2011
Publications
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Correctness Issues on MARTE/CCSL constraintsScience of Computer Programming, 2015, 106, pp.78-92. ⟨10.1016/j.scico.2015.03.001⟩
Article dans une revue
hal-01257978v1
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Logical Time: observation vs. implementationSoftware Engineering Notes, 2011, 36 (1), pp.1--8. ⟨10.1145/1921532.1921554⟩
Article dans une revue
inria-00576647v1
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The Clock Constraint Specification Language for building timed causality modelsInnovations in Systems and Software Engineering, 2010, 6 (1-2), pp.99-106. ⟨10.1007/s11334-009-0109-0⟩
Article dans une revue
inria-00464894v1
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Time in SCChartsForum on specification & Design Languages, Sep 2018, Munich, Germany. pp.5-16, ⟨10.1109/FDL.2018.8524111⟩
Communication dans un congrès
hal-01898285v1
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Explicit Control of Dataflow Graphs with MARTE/CCSLMODELSWARD 2017 - 5th International Conference on Model-Driven Engineering and Software Development, MODELSWARD 2017, Feb 2017, Porto, Portugal. pp.542-549, ⟨10.5220/0006269505420549⟩
Communication dans un congrès
hal-01644294v1
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Execution of Heterogeneous Models for Thermal Analysis with a Multi-view ApproachFDL 2014 : Forum on specification and Design Languages, Oct 2014, Munich, Germany
Communication dans un congrès
hal-01060309v1
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Safe CCSL Specifications and Marked GraphsMEMOCODE - 11th IEEE/ACM International Conference on Formal Methods and Models for Codesign, Oct 2013, Portland, United States. pp.157-166
Communication dans un congrès
hal-00913962v1
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Schedulability analysis with CCSL specificationsAPSEC 2013 - 20th Asia-Pacific Software Engineering Conference, Dec 2013, Bangkok, Thailand. pp.414-421, ⟨10.1109/APSEC.2013.62⟩
Communication dans un congrès
hal-00926305v1
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Combining SystemC, IP-XACT and UML/MARTE in model-based SoC designWorkshop on Model Based Engineering for Embedded Systems Design (M-BED 2011), Mar 2011, Grenoble, France
Communication dans un congrès
inria-00601840v1
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Polychronous Analysis of Timing Constraints in UML MARTEIEEE International Workshop on Model-Based Engineering for Real-Time Embedded Systems Design, May 2010, Parador of Carmona, Spain. 7 p
Communication dans un congrès
inria-00497249v1
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Event-based vs. Time-Triggered Communications with UML MarteForum on specification, verification & Design Languages (FDL'08), ECSI, Sep 2008, Stuttgart, Germany. pp.154-159, ⟨10.1109/FDL.2008.4641438⟩
Communication dans un congrès
inria-00371392v1
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MARTE: A Profile for RT/E Systems Modeling, Analysis (and Simulation?)First International Conference on Simulation Tools and Techniques for Communications, Networks and Systems SIMUTools'08, ICST, Mar 2008, Marseille, France. pp.1-8
Communication dans un congrès
inria-00371397v1
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Dealing with AADL end-to-end Flow Latency with UML Marte.ICECCS - UML&AADL, Apr 2008, Belfast, Ireland. pp.228-233, ⟨10.1109/ICECCS.2008.14⟩
Communication dans un congrès
inria-00371400v1
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Time Modeling in MARTEECSI Forum on specification & Design Languages (FDL), ECSI, Sep 2007, Barcelona, Spain. pp.268-273
Communication dans un congrès
inria-00204481v1
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Modeling Time(s)ACM/IEEE Int. Conf. on Model Driven Engineering Languages and Systems (MoDELS/UML), Oct 2007, Nashville, TN, United States. pp. 559-573, ⟨10.1007/978-3-540-75209-7_38⟩
Communication dans un congrès
inria-00204489v1
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Modeling of Immediate vs. Delayed Data Communications: from AADL to UML MARTEECSI Forum on specification & Design Languages (FDL), ECSI, Sep 2007, Barcelona, Spain. pp.249-254
Communication dans un congrès
inria-00204484v1
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MARTE: a new OMG profile RFP for the Modeling and Analysis of Real-Time Embedded SystemsDAC 2005 Workshop - UML for SoC Design, Jun 2005, Anaheim California, United States
Communication dans un congrès
hal-02466757v1
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Time in SCChartsLanguage, Design Methods, and Tools for Electronic System Design, Springer, pp.1-25, 2019, ⟨10.1007/978-3-030-31585-6_1⟩
Chapitre d'ouvrage
hal-02434885v1
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UML MARTE Time Model and Its Clock Constraint Specification LanguageAlessandra Bagnato; Leandro Soares Indrusiak; Imran Rafiq Quadri; Matteo Rossi. Embedded Systems Design, IGI Global, 2014, Handbook of Research on, 9781466661943. ⟨10.4018/978-1-4666-6194-3.ch002⟩
Chapitre d'ouvrage
hal-01079039v1
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The Time Model of Logical Clocks available in the OMG MARTE profileSandeep K. Shukla and Jean-Pierre Talpin. Synthesis of Embedded Software: Frameworks and Methodologies for Correctness by Construction, Springer Science+Business Media, LLC 2010, pp.28, 2010, 978-1-4419-6399-4
Chapitre d'ouvrage
inria-00495664v1
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MARTE vs. AADL for Discrete-Event and Discrete-Time DomainsMartin Radetzki. Languages for Embedded Systems and their Applications, 36, Springer, pp.27-41, 2009, Lecture Notes in Electrical Engineering, 978-1-4020-9713-3. ⟨10.1007/978-1-4020-9714-0_2⟩
Chapitre d'ouvrage
inria-00416656v1
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Modeling AADL data-communications with UML MARTEEugenio villar. Embedded Systems Specification and Design Languages, 10, Springer, pp.150-170, 2008, Lecture Notes in Electrical Engineering, 978-1-4020-8296-2. ⟨10.1007/978-1-4020-8297-9_11⟩
Chapitre d'ouvrage
inria-00371366v1
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Schedulability analysis by exhaustive state space construction: translating CCSL to transition-based Generalized Buchi Automata[Research Report] RR-8102, 2012, pp.22
Rapport
hal-00743874v1
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Dealing with AADL End-to-end Flow Latency with UML MARTE[Research Report] RR-6402, INRIA. 2008, pp.20
Rapport
inria-00200834v5
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Marte Timing Requirement and Spirit IP-XACT[Research Report] RR-6647, INRIA. 2008
Rapport
inria-00321953v2
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