Frédéric Mallet
Professeur des Universités
Université Côte d'Azur
33
Documents
Affiliations actuelles
- 451999
- 13009
- 478607
- 1039632
Identifiants chercheurs
frederic-mallet- ResearcherId : H-3942-2011
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0000-0002-9088-9821
- IdRef : 060764325
- ResearcherId : http://www.researcherid.com/rid/H-3942-2011
Publications
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Progressive and explicit refinement of scheduling for multidimensional data-flow applications using UML MARTEDesign Automation for Embedded Systems, 2015, 19 (1-2), pp.1-33. ⟨10.1007/s10617-014-9140-y⟩
Article dans une revue
lirmm-01912854v1
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Progressive and explicit refinement of scheduling for multidimensional data-flow applications using uml marteDesign Automation for Embedded Systems, 2012, 16 (2), pp.137-169. ⟨10.1007/s10617-012-9093-y⟩
Article dans une revue
hal-00727239v1
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The Clock Constraint Specification Language for building timed causality modelsInnovations in Systems and Software Engineering, 2010, 6 (1-2), pp.99-106. ⟨10.1007/s11334-009-0109-0⟩
Article dans une revue
inria-00464894v1
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Time in SCChartsForum on specification & Design Languages, Sep 2018, Munich, Germany. pp.5-16, ⟨10.1109/FDL.2018.8524111⟩
Communication dans un congrès
hal-01898285v1
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Explicit Control of Dataflow Graphs with MARTE/CCSLMODELSWARD 2017 - 5th International Conference on Model-Driven Engineering and Software Development, MODELSWARD 2017, Feb 2017, Porto, Portugal. pp.542-549, ⟨10.5220/0006269505420549⟩
Communication dans un congrès
hal-01644294v1
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A Model-Driven Based Environment for Automatic Model CoordinationModels 2015 demo and posters, Oct 2015, Ottawa, Canada
Communication dans un congrès
hal-01198744v1
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A Behavioral Coordination Operator Language (BCOoL)International Conference on Model Driven Engineering Languages and Systems (MODELS), Sep 2015, Ottawa, Canada. pp.462
Communication dans un congrès
hal-01182773v1
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Framework for Heterogeneous Modeling and CompositionConférence en IngénieriE du Logiciel, Jun 2014, Paris, France. pp.81
Communication dans un congrès
hal-01073202v1
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Execution of Heterogeneous Models for Thermal Analysis with a Multi-view ApproachFDL 2014 : Forum on specification and Design Languages, Oct 2014, Munich, Germany
Communication dans un congrès
hal-01060309v1
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Tool Support for the Analysis of TADL2 Timing Constraints using TimeSquareICECCS'2013 - 18th International Conference on Engineering of Complex Computer Systems, Jul 2013, Singapore, Singapore
Communication dans un congrès
hal-00850673v1
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Power consumption analysis using multi-view modelingPATMOS - 23th International Workshop on Power and Timing Modeling, Optimization and Simulation, Sep 2013, Karlsruhe, Germany. pp.235-238, ⟨10.1109/PATMOS.2013.6662180⟩
Communication dans un congrès
hal-00906733v1
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Reifying Concurrency for Executable MetamodelingSLE - 6th International Conference on Software Language Engineering, Oct 2013, Indianapolis, IN, United States. pp.365-384, ⟨10.1007/978-3-319-02654-1_20⟩
Communication dans un congrès
hal-00850770v2
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TimeSquare: Treat your Models with Logical TimeTOOLS - 50th International Conference on Objects, Models, Components, Patterns - 2012, Czech Technical University in Prague, in co-operation with ETH Zurich, May 2012, Prague, Czech Republic. pp.34-41, ⟨10.1007/978-3-642-30561-0_4⟩
Communication dans un congrès
hal-00688590v1
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Multi-View Power Modeling based on UML, MARTE and SysMLSEAA - 38th Euromicro Conference on Software Engineering and Advanced Applications, Sep 2012, Cesme, Turkey. pp.17-20, ⟨10.1109/SEAA.2012.66⟩
Communication dans un congrès
hal-00720735v1
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Logical time and temporal logics: comparing UML MARTE/CCSL and PSL18th International Symposium on Temporal Representation and Reasoning (TIME'11), Sep 2011, Lubeck, Germany
Communication dans un congrès
hal-00597086v1
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A Model-Based Approach for Reconciliation of Polychronous Execution TracesSEAA 2011 - 37th EUROMICRO Conference on Software Engineering and Advanced Applications, Aug 2011, Oulu, Finland
Communication dans un congrès
inria-00597981v1
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Combining SystemC, IP-XACT and UML/MARTE in model-based SoC designWorkshop on Model Based Engineering for Embedded Systems Design (M-BED 2011), Mar 2011, Grenoble, France
Communication dans un congrès
inria-00601840v1
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Logical time @ work: the RT-Simex projectSophia Antipolis Formal Approach, Apr 2011, Sophia, France
Communication dans un congrès
inria-00587151v1
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Semantic Multi-View model for Low-PowerJournées nationales IDM, CAL, et du GDR GPL, Jun 2011, Lille, France. pp.19
Communication dans un congrès
hal-00596239v1
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VHDL Observers for Clock Constraint CheckingSymposium on Industrial Embedded Systems, Jul 2010, trento, Italy. ⟨10.1109/SIES.2010.5551372⟩
Communication dans un congrès
inria-00587107v1
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RT-simex: retro-analysis of execution tracesSIGSOFT FSE, Nov 2010, Santa Fe, United States. pp.377-378, ⟨10.1145/1882291.1882357⟩
Communication dans un congrès
inria-00587116v1
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Logical time at work: capturing data dependencies and platform constraintsForum for Design Languages (FDL), Electronic Chips & Systems design Initiative (ECSI), Sep 2010, Southampton, United Kingdom. pp.240-246
Communication dans un congrès
inria-00545866v1
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Executing AADL models with UML/MarteInt. Conf. Engineering of Complex Computer Systems - ICECCS'09, Jun 2009, Potsdam, Germany. pp. 371-376, ⟨10.1109/ICECCS.2009.10⟩
Communication dans un congrès
inria-00416592v1
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Time in SCChartsLanguage, Design Methods, and Tools for Electronic System Design, Springer, pp.1-25, 2019, ⟨10.1007/978-3-030-31585-6_1⟩
Chapitre d'ouvrage
hal-02434885v1
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UML MARTE Time Model and Its Clock Constraint Specification LanguageAlessandra Bagnato; Leandro Soares Indrusiak; Imran Rafiq Quadri; Matteo Rossi. Embedded Systems Design, IGI Global, 2014, Handbook of Research on, 9781466661943. ⟨10.4018/978-1-4666-6194-3.ch002⟩
Chapitre d'ouvrage
hal-01079039v1
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Logical Time @ Work: Capturing Data Dependencies and Platform ConstraintsKaźmierski, Tom J. J. and Morawiec, Adam. System Specification and Design Languages, 106, Springer New York, pp.223--238, 2012, Lecture Notes in Electrical Engineering, 978-1-4614-1426-1. ⟨10.1007/978-1-4614-1427-8_14⟩
Chapitre d'ouvrage
hal-00651864v1
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The Time Model of Logical Clocks available in the OMG MARTE profileSandeep K. Shukla and Jean-Pierre Talpin. Synthesis of Embedded Software: Frameworks and Methodologies for Correctness by Construction, Springer Science+Business Media, LLC 2010, pp.28, 2010, 978-1-4419-6399-4
Chapitre d'ouvrage
inria-00495664v1
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TimeSquareFrance, Patent n° : IDDN.FR.001.430002.000.S.A.2012.000.10600. 2012
Brevet
hal-01355710v1
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Schedulability analysis by exhaustive state space construction: translating CCSL to transition-based Generalized Buchi Automata[Research Report] RR-8102, 2012, pp.22
Rapport
hal-00743874v1
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ECL: the Event Constraint Language, an Extension of OCL with Events[Research Report] RR-8031, INRIA. 2012, pp.24
Rapport
hal-00721169v2
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Multi-View Power Modeling based on UML MARTE and SysML[Research Report] RR-7934, INRIA. 2012, pp.19
Rapport
hal-00688853v1
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Transforming CCSL partially-ordered Traces into UML Interaction Diagrams[Research Report] RR-7842, INRIA. 2011
Rapport
hal-00652987v1
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Logical time and temporal logics: Comparing UML MARTE/CCSL and PSL[Research Report] RR-7459, INRIA. 2011
Rapport
inria-00540738v2
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