Nombre de documents

49

CV de François Verdier


Article dans une revue6 documents

  • Adrian Voicila, David Declercq, Francois Verdier, Marc Fossorier, Pascal Urard. Low-Complexity Decoding for Non-Binary LDPC Codes in High Order Fields. IEEE Transactions on Communications, Institute of Electrical and Electronics Engineers, 2010, 58 (5), pp.1365-1375. <hal-00521074>
  • Fakhreddine Ghaffari, Benoit Miramond, François Verdier. Run-Time HW/SW Scheduling of Data Flow Applications on Reconfigurable Architectures. EURASIP Journal on Embedded Systems, SpringerOpen, 2009, 2009, pp.976296. <10.1155/2009/976296>. <hal-00524591>
  • Benoit Miramond, Emmanuel Huck, François Verdier, Mohamed El Amine Benkhelifa, Bertrand Granado, et al.. OveRSoC : a Framework for the Exploration of RTOS for RSoC Platforms. International Journal of Reconfigurable Computing, Hindawi Publishing Corporation, 2009, 2009, pp.450607. <10.1155/2009/450607>. <inria-00450258>
  • François Verdier, Benoit Miramond, M. Maillard, Emmanuel Huck, Thomas Lefebvre. Using High-Level RTOS Models for HW/SW Embedded Architecture Exploration : Case Study on Mobile Robotic Vision. EURASIP Journal on Embedded Systems, SpringerOpen, 2008, 2008, pp.349465. <10.1155/2008/349465>. <hal-00524580>
  • François Verdier, Bertrand Zavidovique. A High Level Synthesis System for VLSI Image Processing Applications. International Journal of VLSI Design, 1998, 7 (4), pp.111-121. <hal-00524564>
  • François Verdier, B. Zavidovique. Des architectures intégrées pour la vision : synthèse automatique en trois exemples. Traitement du Signal, Lavoisier, 1997, 14 (2), pp.227-249. <hal-00524601>

HDR1 document

  • François Verdier. Conception d'architectures embarquées : des décodeurs LDPC aux systèmes sur puce reconfigurables. Informatique [cs]. Université de Cergy Pontoise, 2006. <tel-00524534>

Communication dans un congrès36 documents

  • Hend Affes, A. Ben Ameur, Michel Auguin, François Verdier. An ESL framework for low power architecture design space exploration. IEEE International Conference on Application-specific Systems, Architectures and Processors, Jul 2016, Londres, United Kingdom. 2016, IEEE International Conference on Application-specific Systems, Architectures and Processors. <hal-01315340>
  • Calypso Barnes, Jean-Marie Cottin, François Verdier, Alain Pegatoquet, Daniel Gaffé. Developing a Framework Dedicated to Wireless Protocol Property Validation during Simulation. Euromicro Conference on Digital System Design (DSD), Aug 2016, Limassol, Cyprus. pp.Work in Progress session, 2016. <hal-01343907>
  • Emmanuel Vaumorin, Grégoire Avot, Hend Affes, Michel Auguin, Alain Pegatoquet, et al.. Extending IP-XACT and UPF to support ESL to RTL low power design methodology. DAC Workshop on System-to-Silicon Performance Modeling and Analysis, Jun 2015, San Francisco, United States. 2015. <hal-01174345>
  • Calypso Barnes, Jean-Marie Cottin, Enrico Fraccaroli, Stefano Angeleri, Davide Quaglia, et al.. Network-aware Virtual Platform for the Verification of Embedded Software for Communications. 18th Euromicro Conference on Digital Systems Design (DSD 2015), Aug 2015, Madeire, Portugal. pp.518-525, Proc. 18th Euromicro Conference on Digital Systems Design (DSD 2015). <10.1109/DSD.2015.110>. <hal-01287666>
  • Hend Affes, Michel Auguin, François Verdier, Alain Pegatoquet. A Methodology for Inserting Clock-Management Strategies in Transaction-Level Models of System-on-Chips. Forum on specification & Design Languages (FDL), Sep 2015, Barcelone, Spain. pp.1-7, 2015, Proc. Forum on specification & Design Languages (FDL). <hal-01287647>
  • A. Ben Ameur, Hend Affes, Michel Auguin, François Verdier, Xavier Buisson. Clock Management and Analysis for Transaction-Level Virtual Prototypes. Forum on specification & Design Languages (FDL), Sep 2015, Barcelone, Spain. 2015, Proc. Forum on specification & Design Languages (FDL). <hal-01287652>
  • Laurent Gantel, Mohamed El Amine Benkhelifa, François Verdier, Fabrice Lemonnier. MRAPI Implementation for Heterogeneous Reconfigurable Systems-on-Chip. 22nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2014, Boston, MA, United States. pp.239, <10.1109/FCCM.2014.74>. <hal-01329302>
  • Laurent Gantel, Mohamed El Amine Benkhelifa, Fabrice Lemonnier, François Verdier. Module Relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow. International conference on ReConFigurable Computing and FPGAs (ReConFig), Dec 2012, Cancun, Mexico. pp.1-6, 2013. <hal-00794049>
  • Imène Bahri, Eric Monmasson, François Verdier, Mohamed El Amine Benkhelifa. Design and validation methodology of FPGA-based motor drive for High Temperature environment. Electrical Systems for Aircraft, Railway and Ship Propulsion (ESARS), Oct 2010, Bologna, Italy. pp.1 - 6, 2010, <10.1109/ESARS.2010.5665210>. <hal-00670716>
  • Imen Bahri, Eric Monmasson, François Verdier, Mohamed El Amine Benkhelifa. SoPC-based current controler for Permanent Magnet Synchronous Machines drive. IEEE International Symposium on Industrial Electronics (ISIE'10), 2010, Bari, Italy. pp.1, 2010. <hal-00524773>
  • Laurent Gantel, Salah Layouni, Mohamed El Amine Benkhelifa, François Verdier, Stéphanie Chauvet. Multiprocessor Task Migration Implementation in a Reconfigurable Platform. IEEE International Conference on ReConFigurable Computing and FPGAs (ReConFig'09), 2009, Cancun, Mexico. pp.1, 2009. <hal-00524765>
  • Laurent Gantel, Salah Layouni, Mohamed El Amine Benkhelifa, François Verdier. Task Migration in MPSoC Reconfigurable Platforms. Conference on Design and Architectures for Signal and Image Processing (DASIP'09), 2009, Sophia-Antipolis, France. pp.1, 2009. <hal-00524769>
  • David Declercq, Adrian Voicila, François Verdier, Marc Fossorier, Pascal Urard. Architecture of a Non-binary LDPC Decoder for the Next Generation Coding Systems. 26th IEEE International Conference on Consumer Electronics (ICCE), Jan 2008, United States. 2008. <hal-00521915>
  • Gregory Gailliard, Hughes Balp, Christophe Jouvray, François Verdier. Towards a Common HW/SW Interface-centric and Component-oriented Specification and Design Methodology. Forum on Specification and Design Languages (FDL'08), Sep 2008, Stuttgard, Germany. pp.1, 2008. <hal-00524709>
  • Fakhreddine Ghaffari, Benoit Miramond, François Verdier. Dynamic adaptation of Hardware-Software scheduling for Reconfigurable System-on-Chip. 19th IEEE/IFIP International Symposium on Rapid System Prototyping (RSP'08), Jun 2008, Monterey, CA, United States. pp.1, 2008. <hal-00524751>
  • Gregory Gailliard, Hughes Balp, Michel Sarlotte, François Verdier. Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform Components. International Conference on Design and Test in Europe (DATE'08), Mar 2008, Munich, Germany. pp.1, 2008. <hal-00524748>
  • Emmanuel Huck, Benoit Miramond, François Verdier. SystemC multiprocessor RTOS model for services distribution on MPSoC platforms. Conference on Design and Architectures for Signal and Image Processing (DASIP), Nov 2008, Bruxelles, Belgium. pp.1, 2008. <hal-00524756>
  • Adrian Voicila, David Declercq, François Verdier, Marc Fossorier, Pascal Urard. Split non-binary LDPC codes. International Symposium on Information Theory (ISIT'08), Jul 2008, Toronto, Canada. pp.955-959, 2008, <10.1109/ISIT.2008.4595128>. <hal-00524752>
  • Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Bertrand Granado, Emmanuel Huck, Benoit Miramond, et al.. A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources. ReConFig'08, 2008, Mexico. pp.61-66, 2008. <hal-00404919>
  • Adrian Voicila, David Declercq, François Verdier, Marc Fossorier, Pascal Urard. Architecture of a low-complexity non-binary LDPC decoder for high order fields. 7th International Symposium on Communications and Information Technologies (ISCIT'07), Oct 2007, Sydney, Australia. pp.1, 2007. <hal-00524702>
  • Adrian Voicila, David Declercq, François Verdier, Marc Fossorier. Low complexity, Low memory EMS algorithm for non-binary LDPC codes. IEEE International Conference on Communications, Jun 2007, Glasgow, United Kingdom. pp.1, 2007. <hal-00524698>
  • Emmanuel Huck, Benoit Miramond, François Verdier. A Modular SystemC RTOS Model for Embedded Services Exploration. 1st European Workshop on Design and Architectures for Signal and Image Processing (DASIP'07), Nov 2007, Grenoble, France. pp.1, 2007. <hal-00524703>
  • Gregory Gailliard, Bernard Mercier, Michel Sarlotte, Bernard Candaele, François Verdier. Towards a SystemC TLM based Methodology for Platform Design and IP Reuse: Application to Software Radio. Second European Workshop on Reconfigurable Communication-centric SoCs (ReCoSoC'06), Jul 2006, Montpellier, France. pp.1, 2006. <hal-00524631>
  • Arthur Segard, François Verdier, David Declercq, Pascal Urard. A DVB-S2 compliant LDPC decoder integrating the Horizontal Shuffle Scheduling. IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS'06), Dec 2006, Tottori, Japan. pp.1, 2006. <hal-00524692>
  • Gregory Gailliard, Eric Nicollet, Michel Sarlotte, François Verdier. Transaction Level Modelling of SCA compliant Software Defined Radio Waveforms and Platforms PIM/PSM. International Conference on Design and Test in Europe (DATE'06), Apr 2006, Nice, France. pp.1, 2007. <hal-00524695>
  • Imène Benkhermi, Mohamed El Amine Benkhelifa, Daniel Chillet, Sébastien Pillement, Jean-Christophe Prévotet, et al.. System Level Modelling for Reconfigurable SoCs. 20th Conference on Design of Circuits and Integrated Systems (DCIS'05), Nov 2005, Lisboa, Portugal. pp.1, 2005. <hal-00524629>
  • François Verdier, Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Daniel Chillet, Sébastien Pillement. Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. European Workshop on Reconfigurable Communication-centric SoC (ReCoSoC 2005), 2005, Montpellier, France. 2005. <hal-00524777>
  • Arthur Segar, François Verdier. SOC and RTOS: Managing IPs and Tasks Communications. International Conference on Field-Programmable Logic and its Applications (FPL'04), Aug 2004, Antwerp, Belgium. pp.710-718, 2004. <hal-00524625>
  • François Verdier, David Declercq. A LDPC Parity Check Matrix Construction for Parallel Hardware Decoding. 3rd International Symposium on Turbo Codes and Related Topics, Sep 2003, Brest, France. pp.235-238, 2003. <hal-00524620>
  • David Declercq, François Verdier. Optimization of LDPC Finite Precision Belief Propagation Decoding with Discrete Density Evolution. 3rd International Symposium on Turbo Codes and Related Topics, Sep 2003, Brest, France. pp.479-482, 2003. <hal-00524622>
  • François Verdier, A. Mérigot, Bertrand Zavidovique. Fast Stable Matching Algorithm Using Asynchronous Parallel Programming Model. IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'2000), Sep 2000, Padova, Italy. pp.131-135, 2000. <hal-00524618>
  • Ivan Kraljic, François Verdier, Georges Quenot, Bertrand Zavidovique. Investigating Real-Time Validation of Real-Time Image Processing ASICs. IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'97), Oct 1997, Cambridge, MA, United States. pp.116-125, 1997. <hal-00524614>
  • Ivan Kraljic, François Verdier, Georges Quenot, Bertrand Zavidovique. Systematic Design of Image Processing ASICs through Real-Time Emulation. 11th International Conference on Systems Engineering (ICSE'96), Jul 1996, Las Vegas, NA, United States. pp.1, 1996. <hal-00524611>
  • François Verdier, Bertrand Zavidovique. High-Level Synthesis of a Defect Detector. IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'95), Sep 1995, Como, Italy. pp.411-415, 1995. <hal-00524610>
  • François Verdier, Bertrand Zavidovique. A Complete Environment for Global Architecture Synthesis. IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'93), Dec 1993, New Orleans, LA, United States. pp.77-81, 1993. <hal-00524608>
  • François Verdier, Abdelhakim Safir, B. Zavidovique. A High Level Synthesis Algorithm Including Control Constraints. EUROMICRO Conference, 1992, PARIS, France. pp.1, 1992. <hal-00524605>

Poster2 documents

  • Calypso Barnes, Jean-Marie Cottin, François Verdier, Alain Pegatoquet. Modeling a Node’s System-On-Chip for a More Reliable Simulation of Wireless Sensor Networks. Sensors Energy harvesting wireless Network & Smart Objects conference (SENSO), Oct 2014, Aix-en-Provence, France. 2014. <hal-01329305>
  • Calypso Barnes, Jean-Marie Cottin, François Verdier, Alain Pegatoquet. Modeling a Node’s System-On-Chip for a More Reliable Simulation of Wireless Sensor Networks. Journée thématique Energy Aware Network, Labex UCN@SOPHIA, Oct 2014, Sophia Antipolis, France. 2014. <hal-01329304>

Brevet2 documents

  • Adrian Voicila, David Declercq, Marc Fossorier, François Verdier, Pascal Urard. Method and device for encoding symbols with a code of the parity check type and corresponding decoding method and device. United States, Patent n° : US20120173947 A1. 2012. <hal-01329301>
  • Adrian Voicila, David Declercq, Marc Fossorier, François Verdier, Pascal Urard. Procédé et dispositif d'encodage de symboles avec un code du type à contrôle de parité et procédé et dispositif correspondants de décodage. France, N° de brevet: 07-2056FR. 2007. <hal-00524559>

Chapitre d'ouvrage2 documents

  • Benoit Miramond, Emmanuel Huck, Thomas Lefebvre, François Verdier. SystemC Multiprocessor RTOS model for services distribution on RTOS platforms. Springer. Lecture Notes in Electrical Engineering - Algorithm-Architecture Matching for Signal and Image Processing, pp.197-216, 2011, <10.1007/978-90-481-9965-5_9>. <hal-01174353>
  • Bertrand Zavidovique, Christian Fortunel, Georges Quenot, Abdelhakim Safir, Jocelyn Serot, et al.. Automatic synthesis of vision automata. Magdy A. Bayoumi. VLSI Design Methodologies for Digital Signal Processing Architectures, Kluwer Academic Publisher, pp.261-318, 1994. <hal-00524553>