Filtrer vos résultats
- 20
- 12
- 21
- 7
- 2
- 1
- 1
- 7
- 32
- 3
- 1
- 1
- 1
- 2
- 2
- 5
- 7
- 4
- 1
- 1
- 1
- 1
- 2
- 1
- 1
- 1
- 26
- 6
- 32
- 24
- 10
- 9
- 3
- 3
- 2
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 32
- 14
- 10
- 9
- 7
- 7
- 6
- 3
- 3
- 3
- 3
- 3
- 2
- 2
- 2
- 2
- 2
- 2
- 2
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
32 résultats
|
|
|
triés par
|
|
|
A Parallel and Modular Architecture for 802.16e LDPC Codes11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 2008), Sep 2008, Parme, Italy. pp.418 - 421
Communication dans un congrès
inria-00449834v1
|
||
|
|
Panorama des algorithmes efficaces et architectures matérielles pour le filtrage réseau haut débit et la détection d'intrusionsMajecSTIC 2006 : MAnifestation des JEunes Cherchercheurs STIC, Nov 2006, Lorient, France. pp.1-8
Communication dans un congrès
hal-01833585v1
|
||
Graph Constraints in Embedded System DesignWorshop on Combinatorial Optimization for Embedded System Design (COESD 2010), Jun 2010, Bologne, Italy
Communication dans un congrès
inria-00481135v1
|
|||
|
|
Microcode optimization for the PCS processor[Research Report] RR-1050, INRIA. 1989
Rapport
inria-00075509v1
|
||
|
|
Systolic architectures for connected speech recognition[Research Report] RR-0332, INRIA. 1984
Rapport
inria-00076225v1
|
||
Energy Efficient Sensor Node Implementations8th International Symposium on Field-Programmable Gate Arrays (FPGA 2010), Feb 2010, Monterey, United States
Communication dans un congrès
inria-00451689v1
|
|||
Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application CompilationACM Transactions on Reconfigurable Technology and Systems (TRETS), 2012, 5 (2), pp.10:1--10:38. ⟨10.1145/2209285.2209289⟩
Article dans une revue
hal-00663464v1
|
|||
|
|
Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter OptimizationASP-DAC 2021 - 26th Asia and South Pacific Design Automation Conference, Jan 2021, Virtual Conference, Japan. pp.1-6
Communication dans un congrès
hal-03119732v1
|
||
|
|
Efficient parallel non-linear multigrid relaxation algorithms for low-level vision applications[Research Report] RR-2184, INRIA. 1994
Rapport
inria-00074487v1
|
||
|
|
A Generic Architecture of CCSDS Low Density Parity Check Decoder for Near-Earth ApplicationsDesign, Automation & Test in Europe Conference & Exhibition, 2009 (DATE '09), Apr 2009, Nice, France. pp.1242-1245
Communication dans un congrès
inria-00449731v1
|
||
A New High Performance Multi Gigabit String Matching EngineInternational Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2008, Jul 2007, Las Vegas, United States. pp.90-96
Communication dans un congrès
inria-00449847v1
|
|||
Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'10)IEEE Computer Society, pp.355, 2010, 978-1-4244-6967-3
Ouvrages
inria-00554212v1
|
|||
Design Methodology for a High Performance Robust DVB-S2 Decoder Implementation13th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 2010), Sep 2010, Lille, France
Communication dans un congrès
inria-00480723v1
|
|||
|
|
Exploiting Reconfigurable SWP Operators for Multimedia ApplicationsICASSP: International Conference on Acoustics, Speech and Signal Processing, May 2011, Prague, Czech Republic
Communication dans un congrès
inria-00567017v1
|
||
|
|
Exploitation optimale des circuits reconfigurables FPGA pour la mise en oeuvre d'un moteur de recherche de motifs2008
Pré-publication, Document de travail
hal-00202772v2
|
||
How Constraints Programming Can Help You in the Generation of Optimized Application Specific Reconfigurable Processor ExtensionsInternational Conference on Engineering of Reconfigurable Systems & Algorithms (ERSA 2009), Jul 2009, Las Vegas, United States
Communication dans un congrès
inria-00449775v1
|
|||
|
|
A New Powerful Scalable Generic Multi-Standard LDPC Decoder Architecture16th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2008), Apr 2008, Palo Alto, United States. pp.314-315
Communication dans un congrès
inria-00449829v1
|
||
GeCoS: A framework for prototyping custom hardware design flows13th IEEE International Working Conference on Source Code Analysis and Manipulation (SCAM), Sep 2013, Eindhoven, Netherlands. pp.100-105, ⟨10.1109/SCAM.2013.6648190⟩
Communication dans un congrès
hal-00921370v1
|
|||
|
|
Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system20th IEEE International Conference on Application-specific Systems, Architectures and Processors, (ASAP 2009), Jul 2009, Boston, United States. pp.145-152, ⟨10.1109/ASAP.2009.19⟩
Communication dans un congrès
inria-00449747v1
|
||
|
|
Architecture-Driven Synthesis of Reconfigurable Cells12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools (DSD 2009), Aug 2009, Patras, Greece. pp.531-538
Communication dans un congrès
inria-00449757v1
|
||
|
|
SALTO : System for Assembly-Language Transformation and Optimization[Research Report] RR-2980, INRIA. 1996
Rapport
inria-00073718v1
|
||
|
|
Architectures parallèles spécialisées pour le traitement d'image[Rapport de recherche] RR-1978, INRIA. 1993
Rapport
inria-00074694v1
|
||
|
|
Briques de base pour la réalisation d'architectures parallèles specialisées[Rapport de recherche] RR-1977, INRIA. 1993
Rapport
inria-00074696v1
|
||
Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia ArchitectureInternational Journal of Embedded and Real-Time Communication Systems, 2012, 3 (1), pp.1-30. ⟨10.4018/jertcs.2012010101⟩
Article dans une revue
hal-00663458v1
|
|||
|
|
Machine modeling and loop optimization for horizontal microcoded machines[Research Report] RR-1193, INRIA. 1990
Rapport
inria-00075365v1
|
||
|
|
Sélection d'instructions et ordonnancement parallèle simultanés pour la conception de processeurs spécialisésSymposium en Architecture de Machines (Sympa'14), May 2011, St Malo, France
Communication dans un congrès
hal-00640999v1
|
||
|
|
Sélection automatique d'instructions et ordonnancement d'applications basés sur la programmation par contraintes13ème Symposium en Architecture de machines (SympA'13), Sep 2009, Toulouse, France
Communication dans un congrès
inria-00449670v1
|
||
Design of Processor Accelerators with Constraints8th workshop of the Network for Sweden-based researchers and practitioners of Constraint programming, May 2009, Linköping, Sweden
Communication dans un congrès
inria-00449820v1
|
|||
|
|
Scheduling, Binding and Routing System for a Run-Time Reconfigurable Operator Based Multimedia ArchitectureDesign and Architectures for Signal and Image (DASIP), Oct 2010, Edinburgh, United Kingdom
Communication dans un congrès
inria-00539874v1
|
||
Automatic floating-point to fixed-point conversion for DSP code generationProceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems CASES '02, Nov 2002, Grenoble, France. pp.270--276, ⟨10.1145/581630.581674⟩
Communication dans un congrès
inria-00482916v1
|
- 1
- 2