FC
Francis CALMON
76
Documents
Présentation
```
INSA Lyon - Dept. FIMI
Lab. INL - Institut des Nanotechnologies de Lyon (UMR CNRS 5270)
Campus LyonTech - La Doua
1 rue Enrico Fermi
Batiment Irene Joliot Curie - 4ème étage - Bureau 14-041
69622 Villeurbanne cedex
Tel: (33) (0) 4 72 43 61 59
Email: francis.calmon@insa-lyon.fr
http://inl.cnrs.fr
```
Publications
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Indoor Optical Wireless Communication Coverage Optimization Using a SiPM Photoreceiver2023 IEEE Wireless Communications and Networking Conference (WCNC), Mar 2023, Glasgow, United Kingdom. pp.1-6, ⟨10.1109/WCNC55385.2023.10118956⟩
Communication dans un congrès
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Identification of stress factors and degradation mechanisms inducing DCR drift in SPADs2022 IEEE International Integrated Reliability Workshop (IIRW), Oct 2022, South Lake Tahoe, United States. pp.1-5, ⟨10.1109/IIRW56459.2022.10032759⟩
Communication dans un congrès
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Statistical measurements and Monte-Carlo simulations of DCR in SPADsESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), Sep 2022, Milan, Italy. pp.193-196, ⟨10.1109/ESSCIRC55480.2022.9911519⟩
Communication dans un congrès
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Improving the Photon Detection Probability of SPAD implemented in FD-SOI CMOS Technology with light-trapping concept2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), Sep 2021, Caen, France. ⟨10.1109/EuroSOI-ULIS53016.2021.9560684⟩
Communication dans un congrès
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Dark Count Rate in Single-Photon Avalanche Diodes: characterization and modeling studyESSCIRC / ESSDERC 2021 - IEEE 47th European Solid State Circuits Conference, Sep 2021, Grenoble, France. pp.143-146, ⟨10.1109/ESSCIRC53450.2021.9567806⟩
Communication dans un congrès
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An Active Quenching Circuit for a Native 3D SPAD Pixel in a 28 nm CMOS FDSOI TechnologyIEEE NEWCAS 2021, 2021, En ligne, France. ⟨10.1109/NEWCAS50681.2021.9462754⟩
Communication dans un congrès
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Avalanche Transient Simulations of SPAD integrated in 28nm FD-SOI CMOS Technology2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), Sep 2021, Caen, France. ⟨10.1109/EuroSOI-ULIS53016.2021.9560679⟩
Communication dans un congrès
hal-03622067v1
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SPAD FDSOI cell optimization for lower dark count rate achievement2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Sep 2020, Caen, France. pp.1-5, ⟨10.1109/EUROSOI-ULIS49407.2020.9365292⟩
Communication dans un congrès
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An Ultrafast Active Quenching Circuit for SPAD in CMOS 28nm FDSOI Technology2020 IEEE SENSORS, Oct 2020, Rotterdam, Netherlands. pp.1-4, ⟨10.1109/SENSORS47125.2020.9278902⟩
Communication dans un congrès
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Lowering the Dark Count Rate of SPAD Implemented in CMOS FDSOI TechnologyEUROSOI ULIS 2019, Apr 2019, Grenoble, France. ⟨10.1109/EUROSOI-ULIS45800.2019.9041916⟩
Communication dans un congrès
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Body-biasing considerations with SPAD FDSOI: advantages and drawbacksESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC), Sep 2019, Cracow, Poland. pp.210-213, ⟨10.1109/essderc.2019.8901825⟩
Communication dans un congrès
hal-02379994v1
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Integration of SPAD in 28nm FDSOI CMOS technologyESSDERC, 2018, Dresden, Germany. ⟨10.1109/ESSDERC.2018.8486852⟩
Communication dans un congrès
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Pt nanoislands embedded in Al2O3 matrix: from ALD-based fabrication to structural to electrical characterizationEMRS Spring Meeting, Jan 2017, Strasbourg, France
Communication dans un congrès
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PEALD Platinum Nano-island SET Fabrication and Electrical CharacterizationAVS 17th International Conference on Atomic Layer Deposition, Jan 2017, Denver, United States
Communication dans un congrès
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Novel 3D SPAD architecture in an advanced FDSOI technology8th International Workshop on Intelligent Fast Interconnected and Efficient Devices for Frontier Exploitation in Research and Industry (INFIERI), 2016, FermiLab, USA, United States
Communication dans un congrès
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A novel 3D pixel concept for Geiger-mode detection in SOI technologyJoint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2016, Vienna, Austria
Communication dans un congrès
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Development of a 3D silicon coincidence avalanche detector for charged particle tracking in medical applications2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD), Oct 2016, Strasbourg, France. ⟨10.1109/NSSMIC.2016.8069553⟩
Communication dans un congrès
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On the irreversible transformation of Ti/TiOx/Ti junctions under electrical stressEnergy Materials and Nanotechnology, 2016, Prague, Czech Republic
Communication dans un congrès
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Enhancing electrical performances of Metallic DG-SET based circuits by Tunnel junction engineeringJoint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2016, Vienna, Austria
Communication dans un congrès
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Shadow Edge Lithography coupled with ALD growth of Alumina and Platinum Nanoislands Towards the Fabrication of Single Electron TransistorsEMRS Fall Meeting, 2016, Warsaw, Poland
Communication dans un congrès
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A time-integration based quenching circuit for Geiger-mode avalanche diodes2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), Jun 2015, Grenoble, France. ⟨10.1109/NEWCAS.2015.7182007⟩
Communication dans un congrès
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Oxydation locale d’une couche de titane par AFM pour la réalisation de composants mono-électroniques : étude paramétrée de différents modes de types de pointes17èmes Journées Nationales du Réseau Doctoral en Micro-Nanoélectronique, 2014, Lille, France
Communication dans un congrès
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Towards Nano-Computing Blocks Using Room Temperature Double-Gate Single Electron Transistors12th IEEE International New Circuits and Systems Conference (NEWCAS 2014), 2014, Trois-Rivières, Canada
Communication dans un congrès
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Electrical modeling of 3D interconnects: a set of tools under developmentFourth International Workshop on Intelligent Fast Interconnected and Efficient Devices for Frontier Exploitation in Research and Industry, 2014, Madrid, Spain
Communication dans un congrès
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Investigation of Electrical Characteristics of Multi-Gate Bulk nMOSFET29th International Conference on Microelectronics - MIEL 2014, May 2014, Belgrade, Serbia. pp.95 - 98, ⟨10.1109/MIEL.2014.6842094⟩
Communication dans un congrès
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3D Integration of CMOS Image Sensor with Coprocessor Using TSV last and Micro-Bumps TechnologiesIEEE 63rd Electronic Components and Technology Conf., May 2013, Las Vegas, United States. pp.674-682
Communication dans un congrès
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Nano fabrication of oxide patterns using Atomic Force Microscopy on titanium towards the development of Nano devicesICQNM (Seventh International Conference on Quantum, Nano and Micro Technologies), Aug 2013, Barcelone, Spain
Communication dans un congrès
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Experimental Study of a Bulk-Technology Tri-gates nMOSFETColloque du GDR Systemes materiels-logiciels integres, Jun 2013, Lyon, France
Communication dans un congrès
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"Effects of silicon substrate coupling phenomena on signal integrity for RF or high speed communications in 3D-IC."IEEE 62nd Electronic Components and Technology Conf.,, May 2012, San Diego, United States
Communication dans un congrès
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Room temperature double gate single electron transistor based standard cell library2012 IEEE/ACM International Symposium on Nanoscale Architectures, Jul 2012, Amsterdam, France. pp.146-151, ⟨10.1145/2765491.2765518⟩
Communication dans un congrès
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On the use of nanoelectronic logic cells based on metallic Single Electron Transistors2012 13th International Conference on Ultimate Integration on Silicon (ULIS), Mar 2012, Grenoble, France. pp.157-160, ⟨10.1109/ULIS.2012.6193381⟩
Communication dans un congrès
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" Caractérisation des couplages électriques RF par les substrats de silicium en intégration 3D de circuits "JNM'11, May 2011, Brest, France
Communication dans un congrès
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Modélisation RLCG de lignes coplanaires sur un substrat Silicium pour applications CMOS15e Compatibilité Electromagnétique CEM 2010, Apr 2010, Limoges, France
Communication dans un congrès
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"Characterization and Modeling of RF Substrate Coupling Effects due to Vertical Interconnects in 3D Integrated Circuit Stacking "IEEE Signal Propagation on Interconnects,, May 2010, Hidelsheim, Germany
Communication dans un congrès
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“Characterization and Modelling of Substrate Coupling Effects in 3D Integrated Circuit Stacking” Materials for Advanced Metallization, March 7-10, 2010, Mechelen, Belgium.Materials for Advanced Metallization, Mechelen, Belgium., Mar 2010, Mechelen, Belgium
Communication dans un congrès
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"Characterization and Modelling of Substrate Coupling Effects in 3D Integrated Circuit Stacking"Materials for Advanced Metallization, Mar 2010, Mechelen, Belgium
Communication dans un congrès
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Frequency and Time Domain Characterization of Substrate Coupling Effects in 3D Integration StackIEEE Int. Electronics Manufacturing Technology Conf.,, Dec 2010, Melaka, Malaysia
Communication dans un congrès
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" Effets de couplage RF par les substrats de silicium dans les empilements de circuits intégrés 3D "11e Journées Caractérisation Microondes et Matériaux, Apr 2010, Brest, France
Communication dans un congrès
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Predictive High Frequency Effects of Substrate Coupling in 3D Integrated Circuits StackingPredictive High Frequency Effects of Substrate Coupling in 3D Integrated Circuits Stacking, Sep 2009, San Francisco, United States
Communication dans un congrès
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Intrinsic Cut Off Frequency of Si and GaAs Based Resonant Tunneling DiodesInt. Conference on Ultimate Integration of Silicon, Aachen, Mar 2009, Germany. pp.91-94
Communication dans un congrès
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Challenges and Prospects of RF Oscillators Using Silicon Resonant Tunneling DiodesEuropean Solid-State Device Research Conference, Sep 2009, Athènes, Greece. pp.237-241
Communication dans un congrès
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Performances Comparison of Si and GaAs Based Resonant Tunneling DiodesISCS 2008, The International Symposium on Compound Semiconductors, Sep 2008, Grenoble, France
Communication dans un congrès
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3D Silicon Coincidence Avalanche Detector (3D-SiCAD) for Hadrontherapy and Proton Tomography : Preliminary Results on Charged Particle DetectionForum de la Recherche en Cancérologie Auvergne-Rhône-Alpes 2017, Apr 2017, Lyon, France
Poster de conférence
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ALD growth of Platinum Nanoislands on Alumina for Single Electron Transistors ApplicationsALD growth of Platinum Nanoislands on Alumina for Single Electron Transistors Applications, 2016, Paris, France. 2016
Poster de conférence
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On the behavior of electrically stressed Ti/TiOx/Ti junctions fabricated by local anodic oxidationOn the behavior of electrically stressed Ti/TiOx/Ti junctions fabricated by local anodic oxidation, 2015, Lille, France. 2015
Poster de conférence
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Shadow Edge Evaporation for Single Electron TransistorsShadow Edge Evaporation for Single Electron Transistors, 2015, Lyon, France. 2015
Poster de conférence
hal-01489632v1
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Oxydation locale d’une couche de titane par AFM pour la réalisation de composants mono-électroniques : étude paramétrée de différents modes de types de pointesJournées Nationales du Réseau Doctoral en Micro-Nanoélectronique, May 2014, Lille, France
Poster de conférence
hal-02075131v1
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Oxydation par AFM de fines couches métalliques pour la réalisation de composants mono-électroniquesJournées Nationales du Réseau Doctoral en Micro-Nanoélectronique, Jun 2013, Grenoble, France
Poster de conférence
hal-02075185v1
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Comparison of two conductive AFM probes for the local nano-oxidation of Ti thin filmsJournées Nationales sur les Technologies Emergentes en micro-nanofabrication, May 2013, Evian, France
Poster de conférence
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Use of Atomic Force Microscopy towards the Development of Nano Devices by Fabricating Oxide Patterns on Titanium thin FilmFirst French-German Summer School on Noncontact Atomic Force Microscopy, Oct 2013, Porquerolles, France
Poster de conférence
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Elaboration by AFM lithography of nanostructured Ti/TiOx/Ti tunnel junctionEuromat 2013 (European Congress & Exhibition on Advanced Materials and Processes), Sep 2013, Seville, Spain
Poster de conférence
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Mixed-Signal IC Design addressed to Substrate Noise Immunity in Bulk Silicon ; towards 3D circuitsCRC Press, Germany. Mixed-Signal IC Design addressed to Substrate Noise Immunity in Bulk Silicon ; towards 3D circuits, VALORGE, SUN, LORIVAL, CALMON, GONTRAND, 2015
Chapitre d'ouvrage
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