Florent de Dinechin

Yohann Uguen, Florent de Dinechin, Victor Lezaud, Steven Derrien. Application-specific arithmetic in high-level synthesis tools. ACM Transactions on Architecture and Code Optimization, Association for Computing Machinery, 2020, ⟨10.1145/3377403⟩. ⟨hal-02423363v3⟩

Javier Bruguera, Florent de Dinechin. Guest Editors Introduction: Special Section on Computer Arithmetic. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2019, 68 (7), pp.951-952. ⟨10.1109/TC.2019.2918447⟩. ⟨hal-02151757⟩

Anastasia Volkova, Matei Istoan, Florent de Dinechin, Thibault Hilaire. Towards Hardware IIR Filters Computing Just Right: Direct Form I Case Study. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, In press, ⟨10.1109/TC.2018.2879432⟩. ⟨hal-01561052v3⟩

Fatih Ugurdag, Florent de Dinechin, Yılmaz Serhan Gener, Sezer Gören, Laurent-Stéphane Didier. Hardware division by small integer constants. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2017, ⟨10.1109/TC.2017.2707488⟩. ⟨hal-01402252v2⟩

Hatam Abdoli, Hooman Nikmehr, Naser Movahedinia, Florent de Dinechin. Improving Energy Efficiency of OFDM Using Adaptive Precision Reconfigurable FFT. Circuits, Systems, and Signal Processing, Springer Verlag, 2016, ⟨10.1007/s00034-016-0435-z⟩. ⟨hal-01402231⟩

Florent de Dinechin, Pedro Echeverria, Marisa Lopez-Vallejo, Bogdan Pasca. Floating-Point Exponentiation Units for Reconfigurable Computing. ACM Transactions on Reconfigurable Technology and Systems (TRETS), ACM, 2013, 6 (1), pp.4:1--4:15. ⟨10.1145/2457443.2457447⟩. ⟨ensl-00718637⟩

Florent de Dinechin, Christoph Lauter, Jean-Michel Muller, Serge Torres. On Ziv's rounding test. ACM Transactions on Mathematical Software, Association for Computing Machinery, 2013, 39 (4), pp.26. ⟨ensl-00693317v2⟩

Florent de Dinechin. Multiplication by rational constants: LIP research report 2011-3. IEEE Transactions on Circuits and Systems Part 2 Analog and Digital Signal Processing, Institute of Electrical and Electronics Engineers (IEEE), 2012, pp.00. ⟨10.1109/TCSII.2011.2177706⟩. ⟨ensl-00610328v3⟩

Florent de Dinechin, Bogdan Pasca. Designing Custom Arithmetic Data Paths with FloPoCo. IEEE Design & Test, IEEE, 2011, 28, pp.18-27. ⟨ensl-00646282⟩

Florent de Dinechin, Christoph Lauter, Guillaume Melquiond. Certifying the floating-point implementation of an elementary function using Gappa. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2011, 60 (2), pp.242-253. ⟨10.1109/TC.2010.128⟩. ⟨ensl-00200830v2⟩

Jérémie Detrey, Florent de Dinechin. Fonctions élémentaires en virgule flottante pour les accélérateurs reconfigurables. Revue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, Lavoisier, 2008, Architecture des Ordinateurs, 27 (6), pp.673-698. ⟨10.3166/tsi.27.673-698⟩. ⟨inria-00424001⟩

Florent de Dinechin, Jérémie Detrey. A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic. Journal of Signal Processing Systems, Springer, 2007, 49 (1), pp.161-175. ⟨10.1007/s11265-007-0048-7⟩. ⟨ensl-00542212⟩

Jean-Michel Muller, Florent de Dinechin, Christoph Lauter. Fast and correctly rounded logarithms in double precision. RAIRO - Theoretical Informatics and Applications (RAIRO: ITA), EDP Sciences, 2007, 41 (1), pp.85-102. ⟨10.1051/ita:2007003⟩. ⟨ensl-00000007v2⟩

Florent de Dinechin, Jérémie Detrey. Parameterized floating-point logarithm and exponential functions for FPGAs. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2006, 31 (8), pp.537-545. ⟨10.1016/j.micpro.2006.02.008⟩. ⟨ensl-00542213⟩

Florent de Dinechin, Arnaud Tisserand. Multipartite table methods. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2005, 54 (3), pp.319-330. ⟨ensl-00542210⟩

Florent de Dinechin, Luc Forget, Jean-Michel Muller, Yohann Uguen. Posits: the good, the bad and the ugly. CoNGA 2019 - Conference on Next-Generation Arithmetic, Mar 2019, Singapore, Singapore. pp.1-10, ⟨10.1145/3316279.3316285⟩. ⟨hal-01959581v4⟩

Yohann Uguen, Luc Forget, Florent de Dinechin. Evaluating the hardware cost of the posit number system. FPL 2019 - 29th International Conference on Field-Programmable Logic and Applications (FPL), Sep 2019, Barcelona, Spain. pp.106 - 113. ⟨hal-02130912v4⟩

Luc Forget, Yohann Uguen, Florent de Dinechin, David Thomas. A type-safe arbitrary precision arithmetic portability layer for HLS tools. HEART 2019 - International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Jun 2019, Nagasaki, Japan. pp.1-6, ⟨10.1145/3337801.3337809⟩. ⟨hal-02131798v2⟩

Tiago Jost, Andrea Bocco, Yves Durand, Christian Fabre, Florent de Dinechin, et al.. Variable Precision Floating-Point RISC-V Coprocessor Evaluation using Lightweight Software and Compiler Support. CARRV 2019 - Third Workshop on Computer Architecture Research with RISC-V, Jun 2019, Phoenix, AZ, United States. pp.1-6. ⟨hal-02161621⟩

Florent de Dinechin, Silviu-Ioan Filip, Luc Forget, Martin Kumm. Table-Based versus Shift-And-Add constant multipliers for FPGAs. ARITH 2019 - 26th IEEE Symposium on Computer Arithmetic, Jun 2019, Kyoto, Japan. pp.1-8. ⟨hal-02147078⟩

Andrea Bocco, Yves Durand, Florent de Dinechin. SMURF: Scalar Multiple-precision Unum Risc-V Floating-point Accelerator for Scientific Computing. CoNGA 2019 - Conference on Next-Generation Arithmetic, Mar 2019, Singapour, Singapore. pp.1-8, ⟨10.1145/3316279.3316280⟩. ⟨hal-02087098⟩

Florent de Dinechin. Reflections on 10 years of FloPoCo. ARITH 2019 - 26th IEEE Symposium on Computer Arithmetic, Jun 2019, kyoto, Japan. pp.1-3. ⟨hal-02161527⟩

Florent de Dinechin, Maxime Darrin, Antonin Dudermel, Sébastien Michelland, Alban Reynaud. Une architecture minimisant les échanges entre processeur et mémoire. ComPAS 2018 - Conférence d’informatique en Parallélisme, Architecture et Système, Jul 2018, Toulouse, France. pp.1-8. ⟨hal-01959855⟩

Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Johannes Kappauf, Peter Zipf. Karatsuba with Rectangular Multipliers for FPGAs. ARITH 2018 - 25th IEEE International Symposium on Computer Arithmetic, Jun 2018, Amherst, United States. pp.13-20, ⟨10.1109/ARITH.2018.8464809⟩. ⟨hal-01773447⟩

Yohann Uguen, Florent de Dinechin. Exploration architecturale de l'accumulateur de Kulisch. Compas'2017 - Conférence d’informatique en Parallélisme, Architecture et Système, Jun 2017, Sophia Antipolis, France. pp.1-8. ⟨hal-02131977⟩

Andrea Bocco, Yves Durand, Florent de Dinechin. Hardware support for UNUM floating point arithmetic. 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), Jun 2017, Taormina, Italy. pp.93 - 96, ⟨10.1109/PRIME.2017.7974115⟩. ⟨hal-01618698⟩

Yohann Uguen, Florent de Dinechin, Steven Derrien. A high-level synthesis approach optimizing accumulations in floating-point programs using custom formats and operators. 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Apr 2017, Napa, United States. pp.80-80, ⟨10.1109/FCCM.2017.41⟩. ⟨hal-01498357v2⟩

Matei Istoan, Florent de Dinechin. Automating the pipeline of arithmetic datapaths. Design, Automation & Test in Europe Conference & Exhibition (DATE 2017), Mar 2017, Lausanne, Switzerland. ⟨hal-01373937v2⟩

Yohann Uguen, Florent de Dinechin, Steven Derrien. Bridging High-Level Synthesis and Application-Specific Arithmetic: The Case Study of Floating-Point Summations. 27th International Conference on Field-Programmable Logic and Applications (FPL), IEEE, Sep 2017, Gent, Belgium. pp.8. ⟨hal-01373954v2⟩

Matei Istoan, Florent de Dinechin. Pipeline automatique d’opérateurs dans FloPoCo 5.0. COMPAS'2016: Conférence d’informatique en Parallélisme, Architecture et Système, Jul 2016, Lorient, France. ⟨hal-01348007⟩

Julien Le Maire, Nicolas Brunie, Florent de Dinechin, Jean-Michel Muller. Computing floating-point logarithms with fixed-point operations. 23rd IEEE Symposium on Computer Arithmetic, IEEE, Jul 2016, Santa Clara, United States. ⟨hal-01227877⟩

Florent de Dinechin, Matei Istoan. Hardware implementations of fixed-point Atan2. 22nd IEEE Symposium on Computer Arithmetic, Jun 2015, Lyon, France. ⟨hal-01091138⟩

Nicolas Brunie, Florent de Dinechin, Olga Kupriianova, Christoph Lauter. Code generators for mathematical functions. 22d IEEE Symposium on Computer Arithmetic, Jun 2015, Lyon, France. ⟨hal-01084726v2⟩

Florent de Dinechin, Matei Istoan, Albdelbassat Massouri. Sum-of-Product Architectures Computing Just Right. ASAP - Application-specific Systems, Architectures and Processors, Jun 2014, Zurich, Switzerland. ⟨hal-00957609⟩

Nicolas Brunie, Florent de Dinechin, Matei Istoan, Guillaume Sergent. L'arithmétique sur le tas. Symposium en Architectures nouvelles de machines, Jan 2013, France. ⟨ensl-00762990⟩

Nicolas Brunie, Florent de Dinechin, Benoît de Dinechin. Conception d'une matrice reconfigurable pour coprocesseur fortement couplé. Symposium en Architectures nouvelles de machines, Jan 2013, France. ⟨ensl-00763067⟩

Florent de Dinechin, Matei Istoan, Guillaume Sergent. Fixed-Point Trigonometric Functions on FPGAs. Fourth International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Jun 2013, Edimburgh, United Kingdom. pp.1-6. ⟨ensl-00802777⟩

Nicolas Brunie, Florent de Dinechin, Matei Istoan, Guillaume Sergent, Kinga Illyes, et al.. Arithmetic core generation using bit heaps. 23rd International Conference on Field Programmable Logic and Applications, Sep 2013, Porto, Portugal. pp.1-8. ⟨ensl-00738412v2⟩

Eric Dutisseuil, Jean-Marc Tanguy, Adrian Voicila, Rémi Laube, Francois Bore, et al.. 34 Gb/s PDM-QPSK coherent receiver using SiGe ADCs and a single FPGA for digital signal processing. Optical Fiber Communication Conference, Mar 2012, nc, United States. pp.OM3H.7. ⟨ensl-00766801⟩

Florent de Dinechin, Laurent-Stéphane Didier. Table-based division by small integer constants. 8th International Symposium on Applied Reconfigurable Computing (ARC), Mar 2012, Hong Kong, Hong Kong SAR China. pp.53-63, ⟨10.1007/978-3-642-28365-9_5⟩. ⟨ensl-00642145⟩

Florent de Dinechin, Jean-Michel Muller, Bogdan Pasca, Alexandru Plesco. An FPGA architecture for solving the Table Maker's Dilemma. Application-Specific Systems, Architectures and Processors (ASAP), 2011 IEEE International Conference on, Sep 2011, Santa Monica, United States. pp.187-194, ⟨10.1109/ASAP.2011.6043267⟩. ⟨ensl-00640063⟩

Florent de Dinechin. The arithmetic operators you will never see in a microprocessor. 20th IEEE Symposium on Computer Arithmetic, Jul 2011, Tuebingen, Germany. pp.189-190. ⟨ensl-00642164⟩

Nicolas Brunie, Florent de Dinechin, Benoît de Dinechin. Mixed-precision Fused Multiply and Add. 45th Asilomar Conference on Signals, Systems & Computers, Nov 2011, United States. pp.165-169. ⟨ensl-00642157⟩

Florent de Dinechin, Hong Diep Nguyen, Bogdan Pasca. Pipelined FPGA Adders. International Conference on Field Programmable Logic and Applications, Aug 2010, Milano, Italy. pp.422-427, ⟨10.1109/FPL.2010.87⟩. ⟨ensl-00475780v2⟩

Alvaro Vazquez, Florent de Dinechin. Efficient implementation of Parallel BCD Multiplication in LUT-6 FPGAs. 2010 International Conference on Field-Programmable Technology, Dec 2010, Beijing, China. ⟨inria-00546028⟩

Florent de Dinechin, Bogdan Pasca. Floating-point exponential functions for DSP-enabled FPGAs. International Conference on Field-Programmable Technology, Dec 2010, Beijing, China. pp.110-117. ⟨ensl-00506125⟩

Florent de Dinechin, Honoré Takeugming, Jean-Marc Tanguy. A 128-Tap Complex FIR Filter Processing 20 Giga-Samples/s in a Single FPGA. 44th Conference on signals, systems and computers, United States. ⟨ensl-00542950⟩

Florent de Dinechin, Mioara Maria Joldes, Bogdan Pasca, Guillaume Revy. Multiplicative square root algorithms for FPGAs. International Conference on Field Programmable Logic and Applications, Aug 2010, Milano, Italy. pp.14, ⟨10.1109/FPL.2010.112⟩. ⟨ensl-00475779v2⟩

Sebastian Banescu, Florent de Dinechin, Bogdan Pasca, Radu Tudoran. Multipliers for Floating-Point Double Precision and Beyond on FPGAs. Highly Efficient Accelerators and Reconfigurable Technologies, Jun 2010, Tsukuba, Japan. ⟨ensl-00475781v2⟩

Florent de Dinechin, Claude-Pierre Jeannerod, David Pfannholzer, Nathalie Revol. Code generation for argument filtering and argument reduction in elementary functions. SCAN 2010: 14th GAMM-IMACS International Symposium on Scientific Computing, Computer Arithmetic and Validated Numerics, Revol, Nathalie and de Dinechin, Florent and Jeannerod, Claude-Pierre and Lefèvre, Vincent and Louvet, Nicolas and Morin, Sèverine and Nguyen, Hong Diep, Sep 2010, Lyon, France. ⟨inria-00544808⟩

Florent de Dinechin, Mioara Joldes, Bogdan Pasca. Automatic generation of polynomial-based hardware architectures for function evaluation. Application-specific Systems, Architectures and Processors, Jul 2010, Rennes, France. ⟨ensl-00470506⟩

Vincent Lefèvre, Philippe Théveny, Florent de Dinechin, Claude-Pierre Jeannerod, Christophe Mouilleron, et al.. LEMA: Towards a Language for Reliable Arithmetic. International Workshop on Programming Languages for Mechanized Mathematics Systems (PLMMS 2010), Jul 2010, Paris, France. pp.41-52, ⟨10.1145/1838599.1838622⟩. ⟨inria-00542143⟩

Florent de Dinechin, Bogdan Pasca. Large multipliers with less DSP blocks. Field Programmable Logic and Applications, Aug 2009, Czech Republic. ⟨ensl-00356421⟩

Florent de Dinechin, Cristian Klein, Bogdan Pasca. Generating high-performance custom floating-point pipelines. Field Programmable Logic and Applications, Aug 2009, Prague, Czech Republic. ⟨ensl-00379154v2⟩

Florent de Dinechin, Bogdan Pasca, Octavian Creţ, Radu Tudoran. An FPGA-specific Approach to Floating-Point Accumulation and Sum-of-Products. Field-Programmable Technology, Dec 2008, Taipei, Taiwan. ⟨ensl-00268348v3⟩

Nicolas Brisebarre, Florent de Dinechin, Jean-Michel Muller. Integer and Floating-Point Constant Multipliers for FPGAs. International Conference on Application-Specific Systems, Architectures and Processors, 2008, IMEC, Jul 2008, Leuven, Belgium. pp.239-244, ⟨10.1109/ASAP.2008.4580184⟩. ⟨ensl-00269219⟩

Jérémie Detrey, Florent de Dinechin, Xavier Pujol. Return of the hardware floating-point elementary function. 18th Symposium on Computer Arithmetic, Jun 2007, Montpellier, France. pp.161-168. ⟨ensl-00117386⟩

Yohann Uguen, Florent de Dinechin, Steven Derrien. High-level synthesis and arithmetic optimizations. Compas'2016, Jul 2016, Lorient, France. ⟨hal-02131970⟩

Jean-Michel Muller, Nicolas Brunie, Florent de Dinechin, Claude-Pierre Jeannerod, Mioara Joldes, et al.. Handbook of Floating-point Arithmetic (2nd edition). Birkhäuser Basel, pp.1-627, 2018, 978-3319765259. ⟨10.1007/978-3-319-76526-6⟩. ⟨hal-01766584⟩

Jean-Michel Muller, Nicolas Brisebarre, Florent de Dinechin, Claude-Pierre Jeannerod, Vincent Lefèvre, et al.. Handbook of Floating-Point Arithmetic. Birkhauser Boston, pp.572, 2010. ⟨ensl-00379167⟩

Florent de Dinechin, Jean-Michel Muller. Evaluating Elementary Functions. Nicholas Higham. Princeton Companion to Applied Mathematics, Princeton University Press, pp.2, 2014. ⟨ensl-00989001⟩

Florent de Dinechin, Bogdan Pasca. Reconfigurable arithmetic for HPC. Wim Vanderbauwhede and Khaled Benkrid. High-Performance Computing using FPGAs, Springer, 2013. ⟨ensl-00758377⟩

Florent de Dinechin, Milos Ercegovac, Jean-Michel Muller, Nathalie Revol. Digital Arithmetic. Benjamin Wah. Wiley Encyclopedia of Computer Science and Engineering, Wiley, pp.935-948, 2009. ⟨ensl-00542215⟩

Andrea Bocco, Yves Durand, Florent de Dinechin. Method and device for floating point representation with variable precision. France, Patent n° : 1902386. 2019. ⟨hal-02169527⟩

Nicolas Brunie, Florent de Dinechin, Benoît de Dinechin. Mixed-Precision Merged Multiplication and Addition Operator. France, Patent n° : WO/2012/175828. 2012. ⟨hal-01021919⟩

Luc Forget, Yohann Uguen, Florent de Dinechin. Comparing posit and IEEE-754 hardware cost. 2021. ⟨hal-03195756v2⟩

Maxime Christ, Luc Forget, Florent de Dinechin. Lossless Differential Table Compression for Hardware Function Evaluation. 2020. ⟨hal-03040364⟩

Yohann Uguen, Florent de Dinechin. Design-space exploration for the Kulisch accumulator . 2017. ⟨hal-01488916v2⟩

Yohann Uguen, Florent de Dinechin, Steven Derrien. High-Level Synthesis Using Application-Specific Arithmetic: A Case Study. 2017. ⟨hal-01502644⟩

Silviu-Ioan Filip, Matei Istoan, Florent de Dinechin, Nicolas Brisebarre. Automatic generation of hardware FIR filters from a frequency domain specification. 2017. ⟨hal-01308377v2⟩

Florent de Dinechin. On fixed-point hardware polynomials. 2015. ⟨hal-01214739⟩

Florent de Dinechin. A flexible floating-point logarithm for reconfigurable computers. 2010. ⟨ensl-00506122⟩

Florent de Dinechin, Bogdan Pasca. FPGA-Specific Custom Arithmetic Datapath Design. 2010. ⟨ensl-00542396⟩

Florent de Dinechin, Mioara Maria Joldes, Bogdan Pasca, Guillaume Revy. Racines carrées multiplicatives sur FPGA. 2009. ⟨ensl-00388064⟩

Florent de Dinechin, Christoph Lauter. Optimizing polynomials for floating-point implementation. 2008. ⟨ensl-00260563⟩

Florent de Dinechin, Cristian Klein, Bogdan Pasca. Generating high-performance arithmetic operators for FPGAs. 2008. ⟨ensl-00321209⟩

Florent de Dinechin, Jérémie Detrey, Octavian Creţ, Radu Tudoran. When FPGAs are better at floating-point than microprocessors. 2007. ⟨ensl-00174627⟩

Ionuţ Trestian, Octavian Creţ, Laura Creţ, Lucia Văcariu, Radu Tudoran, et al.. FPGA-BASED COMPUTATION OF THE INDUCTANCE OF COILS USED FOR THE MAGNETIC STIMULATION OF THE NERVOUS SYSTEM. 2007. ⟨ensl-00169909⟩

Alvaro Vazquez, Florent de Dinechin. Multi-operand Decimal Adder Trees for FPGAs. [Research Report] RR-7420, INRIA. 2010, pp.20. ⟨inria-00526327⟩

Vincent Lefèvre, Philippe Théveny, Florent de Dinechin, Claude-Pierre Jeannerod, Christophe Mouilleron, et al.. LEMA: Towards a Language for Reliable Arithmetic. [Research Report] RR-7258, INRIA. 2010, pp.15. ⟨inria-00473767⟩

Catherine Daramy-Loirat, David Defour, Florent de Dinechin, Matthieu Gallet, Nicolas Gast, et al.. CR-LIBM A library of correctly rounded elementary functions in double-precision. [Research Report] LIP,. 2006. ⟨ensl-01529804⟩

Florent de Dinechin, Christoph Lauter, Jean-Michel Muller. Fast and correctly rounded logarithms in double-precision. [Research Report] RR-5682, LIP RR-2005-37, INRIA, LIP. 2005, pp.15. ⟨inria-00070331⟩

Florent de Dinechin, Christoph Lauter, Guillaume Melquiond. Assisted verification of elementary functions. RR-5683, INRIA. 2005, pp.17. ⟨inria-00070330⟩

Florent de Dinechin, David Defour, Christoph Lauter. Fast correct rounding of elementary functions in double precision using double-extended arithmetic. [Research Report] RR-5137, LIP RR-2004-10, INRIA, LIP. 2004. ⟨inria-00071446⟩

Jérémie Detrey, Florent de Dinechin. Second Order Function Approximation with a Single Small Multiplication. [Research Report] RR-5140, LIP RR-2004-13, INRIA, LIP. 2004. ⟨inria-00071443⟩

Florent de Dinechin, Nicolas Gast. Towards the post-ultimate libm. [Research Report] RR-5367, LIP RR 2004-47, INRIA, LIP. 2004, pp.18. ⟨inria-00070636⟩

David Defour, Florent de Dinechin, Jean-Michel Muller. A new scheme for table-based evaluation of functions. [Research Report] RR-4637, LIP RR-2002-45, INRIA, LIP. 2002. ⟨inria-00071948⟩

Jérémie Detrey, Florent de Dinechin. Multipartite Tables in JBits for the Evaluation of Functions on FPGA. [Research Report] RR-4305, LIP RR-2001-44, INRIA, LIP. 2001. ⟨inria-00072282⟩

David Defour, Florent de Dinechin, Jean-Michel Muller. Correctly Rounded Exponential Function in Double Precision Arithmetic. [Research Report] RR-4231, INRIA. 2001. ⟨inria-00072387⟩

Florent de Dinechin, Arnaud Tisserand. Some Improvements on Multipartite Table Methods. [Research Report] RR-4059, INRIA. 2000. ⟨inria-00072577⟩

Florent de Dinechin, Wayne Luk, Steve Mckeever. Towards Portable Hierarchical Placement for FPGAs. [Research Report] RR-3776, LIP RR-1999-50, INRIA, LIP. 1999. ⟨inria-00072885⟩

Florent de Dinechin. The Price of Routing in FPGAs. RR-3772, INRIA. 1999. ⟨inria-00072889⟩

Tanguy Risset, Florent de Dinechin, Sophie Robert. Structured Scheduling of Recurrence Equations. [Research Report] RR-3282, INRIA. 1997. ⟨inria-00073406⟩

Florent de Dinechin. Matériel et logiciel pour l'évaluation de fonctions numériques :
précision, performance et validation. Informatique [cs]. Université Claude Bernard - Lyon I, 2007. ⟨tel-00270151⟩