Florent Bruguier
18
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Reducing the Silicon Area Overhead of Counter-Based Rowhammer MitigationsIEEE Computer Architecture Letters, inPress, IEEE Computer Architecture Letters, pp.1-4. ⟨10.1109/LCA.2023.3328824⟩
Article dans une revue
lirmm-04420368v1
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Reducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations18th CryptArchi Workshop, May 2022, Porquerolles, France
Communication dans un congrès
lirmm-03738883v1
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Modeling Rowhammer memory corruption in the gem5 simulatorTHCon 2022 - Toulouse Hacking Conference, Apr 2022, Toulouse, France
Communication dans un congrès
lirmm-03817303v1
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Diminisher: A Linux Kernel based Countermeasure for TAA VulnerabilityCPS4CIP 2021 - 2nd International Workshop on Cyber-Physical Security for Critical Infrastructures Protection, Oct 2021, virtual event, Germany. pp.477-495, ⟨10.1007/978-3-030-95484-0_28⟩
Communication dans un congrès
hal-03372868v1
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Implementing Rowhammer Memory Corruption in the gem5 SimulatorRSP 2021 - 32nd International Workshop on Rapid System Prototyping, Oct 2021, Virtual Event, France. pp.36-42, ⟨10.1109/RSP53691.2021.9806242⟩
Communication dans un congrès
hal-03418858v1
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Virtual Platform to Analyze the Security of a System on Chip at Microarchitectural LevelEuroS&PW 2021 - IEEE European Symposium on Security and Privacy Workshops, Sep 2021, Vienne, Austria. pp.96-102, ⟨10.1109/EuroSPW54576.2021.00017⟩
Communication dans un congrès
hal-03353878v1
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Vulnerability Assessment of the Rowhammer Attack Using Machine Learning and the gem5 Simulator -Work in ProgressSaT-CPS 2021 - ACM Workshop on Secure and Trustworthy Cyber-Physical Systems, Apr 2021, Virtually, United States. pp.104-109, ⟨10.1145/3445969.3450425⟩
Communication dans un congrès
hal-03196090v1
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Transit-Guard: An OS-based Defense Mechanism Against Transient Execution AttacksETS 2021 - 26th IEEE European Test Symposium, May 2021, Bruges (virtual), Belgium. pp.1-2, ⟨10.1109/ETS50041.2021.9465429⟩
Communication dans un congrès
emse-03195702v1
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Improving the Performance of STT-MRAM LLC through Enhanced Cache Replacement PolicyARCS: Architecture of Computing Systems, Apr 2018, Braunschweig, Germany. pp.168-180, ⟨10.1007/978-3-319-77610-1_13⟩
Communication dans un congrès
lirmm-01669254v2
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Evaluation of Heterogeneous Multicore Cluster Architectures Designed for Mobile ComputingReCoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jul 2018, Lille, France. ⟨10.1109/ReCoSoC.2018.8449376⟩
Communication dans un congrès
lirmm-01871273v1
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Performance and Energy Assessment of Last-Level Cache Replacement PoliciesEDiS: Embedded and Distributed Systems, Dec 2017, Oran, Algeria. ⟨10.1109/EDIS.2017.8284032⟩
Communication dans un congrès
lirmm-01651247v1
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Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy ExplorationMCSoC: Embedded Multicore/Many-core Systems-on-Chip, Sep 2016, Lyon, France. pp.201-208, ⟨10.1109/MCSoC.2016.20⟩
Communication dans un congrès
lirmm-01418745v1
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OpenMP scheduling on ARM big.LITTLE architectureMULTIPROG 2016 - 9th International Workshop on Programmability and Architectures for Heterogeneous Multicores, HIPEAC, Jan 2016, Prague, Czech Republic
Communication dans un congrès
lirmm-01377630v1
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Modeling Rowhammer in the gem5 simulatorPoster de conférence lirmm-03817275v1 |
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Implementation of Rowhammer Effect in gem5Poster de conférence hal-03284443v1 |
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Towards a Flexible and Comprehensive Evaluation Approach for Adressing NVM Integration in Cache Hierarchy2021
Pré-publication, Document de travail
lirmm-03341602v1
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Performance and Energy Impact of Enhanced Cache Replacement Policy on STT-MRAM LLC2021
Pré-publication, Document de travail
lirmm-03341604v1
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Deliverable D5.1 – Technical description of the holistic design flow in CONTINUUM[Research Report] Inria Rennes – Bretagne Atlantique; LIRMM (UM, CNRS); Cortus S.A.S. 2019
Rapport
lirmm-03168363v1
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