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47 résultats
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Formalizing the incremental design and verification process of a pipelined protocol converterRSP International Workshop on Rapid System Prototyping, Jun 2006, Chania, Crete, Greece. pp.103-109, ⟨10.1109/RSP.2006.19⟩
Communication dans un congrès
hal-01338249v1
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CTL-property Transformations along an Incremental Design ProcessInternational Journal on Software Tools for Technology Transfer, 2007, 9 (1), pp.77-88. ⟨10.1007/s10009-006-0007-9⟩
Article dans une revue
hal-01195866v1
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Formal verification of a software countermeasure against instruction skip attacksPROOFS 2013, Aug 2013, Santa-Barbara, United States
Communication dans un congrès
emse-00869509v1
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Feasibility Analysis for Robustness Quantification by Symbolic Model CheckingFormal Methods in System Design, 2011, 39 (2), pp.165-184. ⟨10.1007/s10703-011-0121-5⟩
Article dans une revue
istex
hal-01176355v1
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Using VCI in a on-chip system around SPIN networkMIXDES Mixed Design of Integrated Circuits and Systems, Jun 2004, Szczecin, Poland. pp.571-576
Communication dans un congrès
hal-01521120v1
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Automatic Verification of Counter Systems with Ranking FunctionsINFINITY International Symposium on Infinite-Space Systems, 2007, Porto, Portugal
Communication dans un congrès
hal-01334858v1
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CTL-Property Transformations along an Incremental Design ProcessAVOCS 2004 - 4th International Workshop on Automated Verification of Critical Systems, Sep 2004, London, United Kingdom. pp.263-278
Communication dans un congrès
hal-01496206v1
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Assisting Refinement in System on Chip DesignForum on Specification and Design Languages, Sep 2013, Paris, France. pp.1-6
Communication dans un congrès
hal-01216546v1
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A Further Step in the Incremental Design Process: Incorporation of an Increment SpecificationLPAR IEEE International Conference on Logic for Programming Artificial Intelligence and Reasoning, Nov 2006, Phnom Penh, Cambodia. Short paper
Communication dans un congrès
hal-01336653v1
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CTL May Be Ambiguous When Model Checking Moore MachinesCHARME 2003 - 12th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Oct 2003, L'Aquila, Italy. pp.164-169, ⟨10.1007/978-3-540-39724-3_16⟩
Communication dans un congrès
hal-01529835v1
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Time separation of events, an inverse methodLIX Colloquium on emerging Trends in Concurrency Theory, Nov 2006, Palaiseau, France
Communication dans un congrès
hal-01338491v1
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Minimisation de la taille des buffers entre tâches communicantes pour la conception de composants embarqués4ème Congrès de la Société Française de Recherche Opérationnelle et d'Aide à la Décision (ROADEF 2002), Feb 2002, Paris, France. pp.230
Communication dans un congrès
hal-01562012v1
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FSM-based properties and abstraction of componentsIEEE International Symposium on Rapid System Prototyping, Oct 2014, New Delhi, India. pp.37-43, ⟨10.1109/RSP.2014.6966690⟩
Communication dans un congrès
hal-01215913v1
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A tool for automatic detection of deadlocks in wormhole networks on chipACM Transactions on Design Automation of Electronic Systems, 2008, 13 (1), pp.1-8. ⟨10.1145/1297666.1297672⟩
Article dans une revue
hal-01195903v1
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Property-dependant bisimulation for compositional model-checking[Research Report] lip6.1997.028, LIP6. 1997
Rapport
hal-02547642v1
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Design Validation of ZCSP with SPIN[Research Report] lip6.2002.025, LIP6. 2003
Rapport
hal-02545640v1
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Using CTL formulae as component abstraction in a design and verification flowACSD IEEE International Conference on Application of Concurrency to System Design, Jul 2007, Bratislava, Slovakia. pp.80-89, ⟨10.1109/ACSD.2007.76⟩
Communication dans un congrès
hal-01305787v1
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A Tool for Automatic Detection of Deadlock in Wormhole Networks on ChipHLDVT IEEE International High Level Design Validation and Test Workshop, Nov 2006, Monterey, California, United States. pp.203-210, ⟨10.1109/HLDVT.2006.319992⟩
Communication dans un congrès
hal-01338483v1
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Extension des diagrammes de décisions binaires pour la représentation de programmes VHDL en vue de leur vérification[Rapport de recherche] lip6.2000.029, LIP6. 2000
Rapport
hal-02548390v1
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Timed Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed AutomataFormal Methods in System Design, 2009, 34 (1), pp.59-81. ⟨10.1007/s10703-008-0061-x⟩
Article dans une revue
hal-01195912v1
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Fault attack vulnerability assessment of binary codeCryptography and Security in Computing Systems (CS2’19), Jan 2019, Valencia, Spain. pp.13-18, ⟨10.1145/3304080.3304083⟩
Communication dans un congrès
hal-02163152v1
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Electromagnetic fault injection on microcontrollersChip-to-Cloud Security Forum 2013, Sep 2013, Nice, France
Communication dans un congrès
emse-00871686v1
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Data Decision Diagrams for Petri Net analysis23th International Conference on Application and Theory of Petri Nets, Jun 2002, Adelaide, Australia. pp.101-120, ⟨10.1007/3-540-48068-4_8⟩
Communication dans un congrès
istex
hal-01544997v1
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Approche pour l'intégration du raffinement formel dans le processus de conception des SOCJournal Européen des Systèmes Automatisés (JESA), 2011, 45 (1-3), pp.221-236. ⟨10.3166/jesa.45.221-236⟩
Article dans une revue
istex
hal-01195919v1
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Modular Model Checking of VLSI Designs described in VHDLIEEE International Conference on Computer and their Applications, Mar 1998, Honolulu, Hawai, United States. pp.365-368
Communication dans un congrès
hal-01621482v1
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Experimental evaluation of two software countermeasures against fault attacks2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), May 2014, Arlington, United States. pp.112-117, ⟨10.1109/HST.2014.6855580⟩
Communication dans un congrès
emse-01032449v1
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Fault attacks on two software countermeasuresTRUDEVICE 2014, May 2014, Paderborn, Germany
Communication dans un congrès
emse-00998988v1
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An Inverse Method for Parametric Timed AutomataInternational Journal of Foundations of Computer Science, 2009, 20 (5), pp.819-836. ⟨10.1142/S0129054109006905⟩
Article dans une revue
hal-00772641v1
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Quantifying Robustness by Symbolic Model checking1st Hardware Verification Workshop (CAV workshop), Jul 2010, Edinburgh, United Kingdom. pp.1-12
Communication dans un congrès
hal-01292563v1
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Utilisation de Diagrammes de Décision de Données pour la Vérification Fonctionnelle de Systèmes MatérielsMAJECTSTIC 2004 - MAnifestation des JEunes Chercheurs STIC, Oct 2004, Calais, France
Communication dans un congrès
hal-01521138v1
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