Number of documents


Short CV (last updated in may 2017)

Dimitri Galayko was graduated from Odessa State Polytechnic University (Ukraine) in 1998, he received his master degree from Institute of Applied Sciences of Lyon (INSA-LYON, France) in 1999. He made his PhD thesis in the Institute of Microelectronics and Nanotechnologies (IEMN, Lille, France) and received the PhD degree from the University Lille-I in 2002. The topic of his PhD dissertation was modeling and design of microelectromechanical silicon filters and resonators for radio communications. Since 2005 he is an associate professor in University Paris VI (UPMC, Sorbonne Universités) in the Laboratory of Computer Science (LIP6). He obtained the HDR diploma from UPMC at 2012.

He was a coordinator of two French national collaborative research grants (ANR), HODISS (Architectures du futur program, 2009-2012) et HERODOTOS (Arpege program, 2011-2014). Since 2012 he is expert French Observatory of Micro- and Nano Technologies at the Energy group.  He has supervised 9 PhD students.  His publication record is 23 articles in international journals, 70 communications in international conferences and 4 patents, in addition to invited lectures, tutorials and presentations. He is reviewer in journals such as IEEE TCAS, JMM, Sensor and Actuators. He is an active member of the Technical Committee Nonlinear Circuits and Systems of IEEE CAS society. He has served as:

-  Associate editor at the TCAS-II journal since 2016

- Technical program committee member at PowerMEMS 2016 conference,

- Track co-chair at the ISCAS 2017 conference (appointed by election)

- Track co-chair of the section NCAS at ICECS 2014 in Marseille, 

- Review committee member at ISCAS 2015

He organized a tutorial on electrostatic vibration energy harvesters at ICECS 2014 and several special (invited) sessions at the CAS conferences. 

His research interests cover design and modeling of heterogeneous systems involving a combination of classical CMOS integrated circuit with physical sensors such as MEMS devices and energy harvesters, study of different aspects of oscillating structures in microelectronics (both solid-state CMOS oscillators and MEMS oscillators), and investigation and modeling of nonlinear phenomena emerging in such systems.

Design and modeling of systems for vibration energy harvesting has been one of his main research topics since 2007, on which he collaborates with Circuits and Systems group at University College Dublin, Ireland and with Microsystem group of the ESYCOM laboratory of the University of Paris-Est, France. 

"Chuan Shan"   

Conference papers9 documents

  • Koskin Eugene, Elena Blokhina, Chuan Shan, Eldar Zianbetov, Orla Feely, et al.. Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks. New Circuits and Systems Conference (NEWCAS), 2016 14th IEEE International, IEEE-CASS, Jun 2016, Vancouver, BC, Canada. ⟨10.1109/NEWCAS.2016.7604784⟩. ⟨hal-01521744⟩
  • Chuan Shan, Eldar Zianbetov, François Anceau, Olivier Billoint, Dimitri Galayko. A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs. New Circuits and Systems Conference (NEWCAS), 2015 IEEE 13th International, IEEE-CASS, Jun 2015, Grenoble, France. ⟨10.1109/NEWCAS.2015.7182059⟩. ⟨hal-01521883⟩
  • Chuan Shan, Dimitri Galayko, François Anceau, Eldar Zianbetov. A reconfigurable distributed architecture for clock generation in large many-core SoC. Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9th International Symposium on, May 2014, Montpellier, France. pp.1-8, ⟨10.1109/ReCoSoC.2014.6861349⟩. ⟨hal-01053765⟩
  • Chuan Shan, François Anceau, Dimitri Galayko, Eldar Zianbetov. Swimming pool like distributed architecture for clock generation in large many-core SoC. International Symposium on Circuits and Systemss, 2014, Jun 2014, Melbourne, Australia. pp.2768 - 2771, ⟨10.1109/ISCAS.2014.6865747⟩. ⟨hal-01080071⟩
  • Eldar Zianbetov, Dimitri Galayko, François Anceau, Mohammad Javidan, Chuan Shan, et al.. Distributed clock generator for synchronous SoC using ADPLL network. CICC 2013 - IEEE 2013 Custom Integrated Circuits Conference, Sep 2013, San José, CA, United States. pp.1-4, ⟨10.1109/CICC.2013.6658437⟩. ⟨hal-01053768⟩
  • Chuan Shan, Dimitri Galayko, François Anceau. On-chip clock error characterization for clock distribution system. VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on, Aug 2013, Natal, Brazil. pp.102-108, ⟨10.1109/ISVLSI.2013.6654630⟩. ⟨hal-01053759⟩
  • Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, et al.. FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation. Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on, Dec 2013, Cancun, Mexico. pp.1 - 6, ⟨10.1109/ReConFig.2013.6732295⟩. ⟨hal-01053762⟩
  • Chuan Shan, Dimitri Galayko, François Anceau. Design and Modeling of ADPLL with sliding-window for wide range frequency tracking. New Circuits and Systems Conference (NEWCAS), 2012 IEEE 10th International, Jun 2012, Montreal, Canada. pp.269 - 272, ⟨10.1109/NEWCAS.2012.6329008⟩. ⟨hal-01053756⟩
  • Chuan Shan, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, et al.. FPGA implementation of reconfigurable ADPLL network for distributed clock generation. FTP 2011 - International Conference on Field Programmable Technology, Dec 2011, New Delhi, India. pp.1-4, ⟨10.1109/FPT.2011.6132670⟩. ⟨hal-01053755⟩