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David Novo
10
Documents
Identifiants chercheurs
- david-novo
- 0000-0002-5510-4152
- Google Scholar : https://scholar.google.fr/citations?user=9U2rzRQAAAAJ&hl=en&oi=ao
- IdRef : 244276455
Présentation
Publications
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Multi-level Analysis of GPU Utilization in ML Training Workloads2024 Design, Automation & Test in Europe Conference (DATE 2024), Mar 2024, Valencia (Espagne), Spain
Communication dans un congrès
hal-04523554v1
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Pref-X: a framework to reveal data prefetching in commercial in-order coresDAC 2022 - 59th ACM/IEEE Design Automation Conference, Jul 2022, San Francisco, CA, United States. pp.1051-1056, ⟨10.1145/3489517.3530569⟩
Communication dans un congrès
lirmm-03767077v1
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Demystifying the TensorFlow Eager Execution of Deep Learning Inference on a CPU-GPU TandemDSD 2022 - 25th Euromicro Conference on Digital System Design, Aug 2022, Maspalomas, Spain. pp.446-455, ⟨10.1109/DSD57027.2022.00066⟩
Communication dans un congrès
lirmm-03775613v2
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Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate SimulationDATE 2021 - 24th Design, Automation and Test in Europe Conference and Exhibition, Feb 2021, Grenoble (Virtual), France. pp.707-710, ⟨10.23919/DATE51398.2021.9474108⟩
Communication dans un congrès
lirmm-03084343v1
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Improving the Performance of STT-MRAM LLC through Enhanced Cache Replacement PolicyARCS: Architecture of Computing Systems, Apr 2018, Braunschweig, Germany. pp.168-180, ⟨10.1007/978-3-319-77610-1_13⟩
Communication dans un congrès
lirmm-01669254v2
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Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworksDATE 2018 - 21st Design, Automation and Test in Europe Conference and Exhibition, Mar 2018, Dresden, Germany. pp.103-108, ⟨10.23919/DATE.2018.8341987⟩
Communication dans un congrès
lirmm-01912824v1
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OpenMP scheduling on ARM big.LITTLE architectureMULTIPROG 2016 - 9th International Workshop on Programmability and Architectures for Heterogeneous Multicores, HIPEAC, Jan 2016, Prague, Czech Republic
Communication dans un congrès
lirmm-01377630v1
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Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy ExplorationMCSoC: Embedded Multicore/Many-core Systems-on-Chip, Sep 2016, Lyon, France. pp.201-208, ⟨10.1109/MCSoC.2016.20⟩
Communication dans un congrès
lirmm-01418745v1
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Performance and Energy Impact of Enhanced Cache Replacement Policy on STT-MRAM LLC2021
Pré-publication, Document de travail
lirmm-03341604v1
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Emerging NVM Technologies in Main Memory for Energy-Efficient HPC: an Empirical Study2019
Pré-publication, Document de travail
lirmm-02135043v1
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