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David Novo
12
Documents
Identifiants chercheurs
- david-novo
- 0000-0002-5510-4152
- Google Scholar : https://scholar.google.fr/citations?user=9U2rzRQAAAAJ&hl=en&oi=ao
- IdRef : 244276455
Présentation
Publications
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Improving the Performance of STT-MRAM LLC through Enhanced Cache Replacement PolicyARCS: Architecture of Computing Systems, Apr 2018, Braunschweig, Germany. pp.168-180, ⟨10.1007/978-3-319-77610-1_13⟩
Communication dans un congrès
lirmm-01669254v2
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Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworksDATE 2018 - 21st Design, Automation and Test in Europe Conference and Exhibition, Mar 2018, Dresden, Germany. pp.103-108, ⟨10.23919/DATE.2018.8341987⟩
Communication dans un congrès
lirmm-01912824v1
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Evaluation of Heterogeneous Multicore Cluster Architectures Designed for Mobile ComputingReCoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jul 2018, Lille, France. ⟨10.1109/ReCoSoC.2018.8449376⟩
Communication dans un congrès
lirmm-01871273v1
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Performance and Energy Assessment of Last-Level Cache Replacement PoliciesEDiS: Embedded and Distributed Systems, Dec 2017, Oran, Algeria. ⟨10.1109/EDIS.2017.8284032⟩
Communication dans un congrès
lirmm-01651247v1
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A Workflow for Fast Evaluation of Mapping Heuristics Targeting Cloud InfrastructuresDREAMCloud: Dynamic Resource Allocation and Management in Embedded, High Performance and Cloud Computing, Jan 2016, Prague, Czech Republic
Communication dans un congrès
lirmm-01265874v1
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Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy ExplorationMCSoC: Embedded Multicore/Many-core Systems-on-Chip, Sep 2016, Lyon, France. pp.201-208, ⟨10.1109/MCSoC.2016.20⟩
Communication dans un congrès
lirmm-01418745v1
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Speed and Accuracy Dilemma in NoC Simulation: What about Memory Impact?ReCoSoC: Reconfigurable Communication-centric Systems-on-Chip, Jun 2016, Tallinn, Estonia
Communication dans un congrès
lirmm-01332702v1
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OpenMP scheduling on ARM big.LITTLE architectureMULTIPROG 2016 - 9th International Workshop on Programmability and Architectures for Heterogeneous Multicores, HIPEAC, Jan 2016, Prague, Czech Republic
Communication dans un congrès
lirmm-01377630v1
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Performance and Energy Impact of Enhanced Cache Replacement Policy on STT-MRAM LLC2021
Pré-publication, Document de travail
lirmm-03341604v1
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Towards a Flexible and Comprehensive Evaluation Approach for Adressing NVM Integration in Cache Hierarchy2021
Pré-publication, Document de travail
lirmm-03341602v1
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Emerging NVM Technologies in Main Memory for Energy-Efficient HPC: an Empirical Study2019
Pré-publication, Document de travail
lirmm-02135043v1
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Deliverable D5.1 – Technical description of the holistic design flow in CONTINUUM[Research Report] Inria Rennes – Bretagne Atlantique; LIRMM (UM, CNRS); Cortus S.A.S. 2019
Rapport
lirmm-03168363v1
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