Nombre de documents

18

CV de Daniela Genius


Communication dans un congrès15 documents

  • Daniela Genius, Letitia Li, Ludovic Apvrille. Model-Driven Performance Evaluation and Formal Verification for Multi-level Embedded System Design. Springer. Modeling Languages, Tools and Architectures, Methodologies, Processes and Platforms, Applications and Software Development, Feb 2017, Porto, Portugal. Modeling Languages, Tools and Architectures, Methodologies, Processes and Platforms, Applications and Software Development (MODELSWARD), 2017, <http://www.modelsward.org/Home.aspx>. <hal-01447148>
  • Daniela Genius, Ludovic Apvrille. Virtual Yet Precise Prototyping: An Automotive Case Study. 8th European Congress on Embedded Real Time Software and Systems (ERTS 2016), Jan 2016, TOULOUSE, France. Proceedings of the 8th European Congress on Embedded Real Time Software and Systems (ERTS 2016), pp.691-700, <http://www.erts2016.org/>. <hal-01291888>
  • Daniela Genius. Measuring Memory Latency for Software Objects in a NUMA System-on-Chip Architecture. 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013, Jul 2013, Darmstadt, Germany. IEEE, pp.1-8, <10.1109/ReCoSoC.2013.6581525>. <hal-01216503>
  • Daniela Genius, Khouloud Zine El Abidine. A Hierarchical Approach to the Out-of-order Arrival of Frames in Video Streaming Applications on Clustered MPSoC. International Conference on Design and Architecture for Signal and Image Processing, Oct 2012, Karlsruhe, Germany. IEEE, International Conference on Design and Architecture for Signal and Image Processing, pp.1-8. <hal-01273248>
  • Daniela Genius, Khouloud Zine El Abidine. Handling Out-of-order Arrival for Parallel Streaming Applications on Clustered MPSoC. Conference on Design of Circuits and Integrated Systems, Nov 2012, Avignon, France. Conference on Design of Circuits and Integrated Systems. <hal-01282440>
  • Daniela Genius, Khouloud Zine El Abidine. A Solution to the Data Re-ordering Problem for Multi-Pipeline Streaming Applications on Clustered MPSoC. 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Jul 2012, York, United Kingdom. IEEE, 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp.1-8, <10.1109/ReCoSoC.2012.6322892>. <hal-01272441>
  • Daniela Genius, Nicolas Pouillon. Monitoring Software Communication Channels on a Shared Memory Multi-Processor System on Chip. ReCoSoC Reconfigurable Communication-centric SoCs, Jun 2011, Montpellier, France. IEEE, ReCoSoC Reconfigurable Communication-centric SoCs, pp.1-8, <10.1109/ReCoSoC.2011.5981502>. <hal-01285660>
  • Daniela Genius, Nicolas Pouillon. Analyzing Software Inter-Task Communication Channels on a Clustered Shared Memory Multi Processor +System-on-Chip. International Conference on Design and Architectures for Signal and Image Processing, Nov 2011, Tampere, Finland. IEEE, International Conference on Design and Architectures for Signal and Image Processing, pp.1-8, <10.1109/DASIP.2011.6136892>. <hal-01286023>
  • Daniela Genius, Alix Munier-Kordon, Khouloud Zine El Abidine. A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor. Euro-Par European Conference on Parallel computing, Aug 2009, Delft, Netherlands. Springer, Euro-Par European Conference on Parallel computing, 5704, pp.216-227, Lecture Notes in Computer Science. <10.1007/978-3-642-03869-3_23>. <hal-01294429>
  • Alain Greiner, Etienne Faure, Nicolas Pouillon, Daniela Genius. A Generic Hardware / Software Communication Middleware for Streaming Applications on Shared Memory Multi Processor Systems-on-Chip. FDL Forum on Specification & Design Languages, Sep 2009, Nice, France. FDL Forum on Specification & Design Languages, pp.1-4. <hal-01295103>
  • Etienne Faure, Daniela Genius. Telecommunication Application Modelling with Multi Writer Multi Reader Channels: a Case Study. FDL Forum on Specification & Design Languages, Sep 2008, Stuttgart, Germany. IEEE, FDL Forum on Specification & Design Languages, pp.241-242, <10.1109/FDL.2008.4641455>. <hal-01299160>
  • Daniela Genius, Nicolas Pouillon, Alain Greiner. Design Space Explorer : Un Outil de Co-Conception pour Plate-formes Multi-processeurs sur Puce. CNFM Coordination Nationale pour la Formation en Micro-nanoélectronique, Nov 2008, St Malo, France. CNFM Coordination Nationale pour la Formation en Micro-nanoélectronique, pp.33-38. <hal-01301525>
  • Daniela Genius, Etienne Faure, Nicolas Pouillon. Deploying a Telecommunication on Multiprocessor Systems-on-Chip. International Conference on Design and Architectures for Signal and Image Processing, Nov 2007, Grenoble, France. International Conference on Design and Architectures for Signal and Image Processing, pp.1-8. <hal-01308167>
  • Etienne Faure, Alain Greiner, Daniela Genius. A generic hardware/software communication mechanism for Multi-Processor System on Chip, Targeting Telecommunication Applications. ReCoSoC Reconfigurable Communication-centric SoCs, Jul 2006, Montpellier, France. ReCoSoC Reconfigurable Communication-centric SoCs, pp.237-242. <hal-01338252>
  • Saifeddine Berrayana,, Etienne Faure, Daniela Genius, Frédéric Pétrot. Modular on chip multi processor for routing applications. M. Danelutto, D. Laforenza, M. Vannesch. EuroPar 2004, 2004, Pise, Italy. Springer LNCS, 3149, pp.847-855, Proceedings EuroPar 2004. <hal-01365379>

Article dans une revue1 document

  • Daniela Genius, Alix Munier-Kordon, Khouloud Zine El Abidine. Space Optimal Solution for Data Reordering in Streaming Applications on NoC based MPSoC. Journal of Systems Architecture, Elsevier, 2013, 59 (7), pp.455-467. <10.1016/j.sysarc.2013.04.001>. <hal-01195936>

Poster1 document

  • Letitia Li, Ludovic Apvrille, Daniela Genius. Virtual Prototyping of Automotive Systems: Towards Multi-level Design Space Exploration. Conference on Design and Architectures for Signal and Image Processing, Oct 2016, Rennes, France. 2016. <hal-01365609>

Chapitre d'ouvrage1 document

  • Daniela Genius, Etienne Faure, Nicolas Pouillon. Mapping a Telecommunication Application on a Multiprocessor System-on-Chip. Algorithm-Architecture Matching for Signal and Image Processing, 73, Springer LNEE, pp.53-77, 2011, Lecture Notes in Electrical Engineering, 978-90-481-9964-8. <10.1007/978-90-481-9965-5_3>. <hal-01287781>