Nombre de documents

83

CV de Daniel Chillet


Article dans une revue12 documents

  • Robin Bonamy, Sébastien Bilavarn, Daniel Chillet, Olivier Sentieys. Power Modeling and Exploration of Dynamic and Partially Reconfigurable Systems. Journal of Low Power Electronics, American Scientific Publishers, 2016. <hal-01345664>
  • Robin Bonamy, Sebastien Bilavarn, Daniel Chillet, Olivier Sentieys. Power Consumption Models for the Use of Dynamic and Partial Reconfiguration. Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), Elsevier, 2014, <10.1016/j.micpro.2014.01.002>. <hal-00941532>
  • Rabie Ben Atitallah, Eric Senn, Daniel Chillet, Mickael Lanoe, Dominique Blouin. An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC. IEEE Transactions on Industrial Informatics, Institute of Electrical and Electronics Engineers, 2013, 9 (1), pp.487-501. <10.1109/TII.2012.2198657>. <hal-00921900>
  • Daniel Chillet, Antoine Eiche, Sébastien Pillement, Olivier Sentieys. Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network. Journal of System Architectures, Elsevier North-Holland, Inc., 2011, 57, pp.340-353. <10.1016/j.sysarc.2011.01.004>. <hal-00650650>
  • Dominique Blouin, Daniel Chillet, Eric Senn, Sebastien Bilavarn, Robin Bonamy, et al.. AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC. International Journal of Reconfigurable Computing, Hindawi Publishing Corporation, 2011, Article ID 425401, 15 p. <10.1155/2011/425401>. <hal-00650628>
  • Ludovic Devaux, Sana Ben Sassi, Sebastien Pillement, Daniel Chillet, Didier Demigny. Flexible interconnection network for dynamically and partially reconfigurable architectures. International Journal on Reconfigurable Computing (IJRC), Hindawi Publishing Corporation, 2010. <inria-00437763>
  • Daniel Chillet, Eric Senn, Olivier Zendra, Cécile Belleudy, Smail Niar, et al.. Open Power and Energy Optimization Platform and Estimator (Open-People) ANR Project. Hipeac info 24, Compilation Architecture, HiPEAC Network of Excellence, 2010, pp.16. <inria-00542951>
  • Benoit Miramond, Emmanuel Huck, François Verdier, Mohamed El Amine Benkhelifa, Bertrand Granado, et al.. OveRSoC : a Framework for the Exploration of RTOS for RSoC Platforms. International Journal of Reconfigurable Computing, Hindawi Publishing Corporation, 2009, 2009, pp.450607. <10.1155/2009/450607>. <inria-00450258>
  • Daniel Chillet, Sébastien Pillement, Olivier Sentieys. Ordonnancement de tâches par réseaux de neurones pour architectures de SoC hétérogènes. Traitement du Signal, Lavoisier, 2009, 26 (1), pp.77-89. <inria-00430944>
  • Daniel Chillet, Raphael David, Erwan Grace, Olivier Sentieys. Structure mémoire reconfigurable : vers une structure de stockage faible consommation. Revue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, Lavoisier, 2008, 27 (1), pp.183-204. <inria-00450263>
  • Daniel Menard, Daniel Chillet, Olivier Sentieys. Floating-to-fixed-point Conversion for Digital Signal Processors. Eurasip Journal on Applied Signal Processing, Hindawi Publishing Corporation, 2006, 2006 (1), pp.1-15. <10.1155/ASP/2006/96421>. <inria-00459212>
  • Jean-Philippe Diguet, Olivier Sentieys, Daniel Chillet. A Framework for High Level Estimations of Signal Processing VLSI Implementations. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Springer, 2000, Vol.25 No.3, pp.261 - 284. <10.1023/A:1008191708726>. <hal-00089488>

Communication dans un congrès67 documents

  • Cedric Killian, Daniel Chillet, Sébastien Le Beux, Olivier Sentieys, Van Dung Pham, et al.. Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques. DAC 2017 - IEEE/ACM Design Automation Conference DAC, Jun 2017, Austin, United States. pp.6, 2017. <hal-01495468>
  • Jiating Luo, A Elantably, D Pham, C Killian, Daniel Chillet, et al.. Performance and Energy Aware Wavelength Allocation on Ring-Based WDM 3D Optical NoC. Design, Automation & Test in Europe Conference & Exhibition (DATE) 2017, Mar 2017, Lausanne, Switzerland. <hal-01416958>
  • Aymen Gammoudi, Adel Benzina, Mohamed Khalgui, Daniel Chillet. New Reconfigurable Middleware for Adaptive RTOS in Ubiquitous Devices. 10th International Conference on Mobile Ubiquitous Computing, Systems, Services and Technologies, Oct 2016, Venise, Italy. <hal-01401716>
  • Aymen Gammoudi, Adel Benzina, Mohamed Khalgui, Daniel Chillet. Real-Time Scheduling of Reconfigurable Battery-Powered Multi-Core Platforms. 28th International Conference on Tools with Artificial Intelligence, Nov 2016, San Jose, United States. 2016. <hal-01401712>
  • Van Dung Pham, Daniel Chillet, Cédric Killian, Sébastien Le Beux, Ian O 'Connor, et al.. Gestion de la consommation d'un ONoC intégré dans un MPSoC. Colloque National du GDR SoC-SiP, Jun 2016, Nantes, France. <hal-01414341>
  • Olivier Sentieys, Johanna Sepúlveda, Sébastien Le Beux, Jiating Luo, Cedric Killian, et al.. Design Space Exploration of Optical Interfaces for Silicon Photonic Interconnects. 2th International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop), co-located with IEEE/ACM Design Automation and Test in Europe (DATE’16), Mar 2016, Dresden, Germany. 2016. <hal-01293506>
  • Aymen Gammoudi, Adel Benzina, Mohamed Khalgui, Daniel Chillet, Aicha Goubaa. Reconf-Pack: A Simulator for Reconfigurable Battery-Powered Real-Time Systems. 30th European Simulation and Modelling Conference, Oct 2016, Las Palmas, Spain. 2016. <hal-01401706>
  • Jiating Luo, Daniel Chillet, Cédric Killian, Sébastien Le Beux, Ian O 'Connor, et al.. Crosstalk noise aware wavelength allocation in WDM 3D ONoC. Colloque National du GDR SoC-SiP, Jun 2016, Nantes, France. 2016. <hal-01406355>
  • Jiating Luo, Daniel Chillet, Cédric Killian, Sébastien Le Beux, Ian O 'Connor, et al.. Wavelength spacing optimization to reduce crosstalk in WDM 3D ONoC. Conférence d’informatique en Parallélisme, Architecture et Système, Jul 2016, Lorient, France. 2016. <hal-01406341>
  • Van Dung Pham, Cédric Killian, Daniel Chillet, Sébastien Le Beux, Olivier Sentieys, et al.. Gestion de la consommation d'un réseau optique intégré dans un MPSoC. Conférence d’informatique en Parallélisme, Architecture et Système, Jul 2016, Lorient, France. 2016. <hal-01406347>
  • Ayman Gammoudi, Adel Benzina, Mohamed Khalgui, Daniel Chillet. New Pack Oriented Solutions for Energy-Aware Feasible Adaptive Real-Time Systems. International Conference on Intelligent Software Methodologies, Tools and Techniques, SoMeT 15, Sep 2015, Naples, Italy. <10.1007/978-3-319-22689-7_6>. <hal-01241877>
  • Luo Jiating, Cédric Killian, Sébastien Le Beux, Daniel Chillet, Hui Li, et al.. Channel allocation protocol for reconfigurable Optical Network-on-Chip. SiPhotonics: Exploiting Silicon Photonics for energy-efficient high-performance computing (SiPhotonics'15), Jan 2015, Amsterdam, Netherlands. pp.7, 2015. <hal-01096537>
  • Daniel Chillet, Chin Dinh Ma, Olivier Sentieys. Gestion des zones en fautes d’une architecture reconfigurable lors du placement des tâches matérielles. Gretsi 2015, Sep 2015, Lyon, France. 2015. <hal-01193179>
  • Martha Johanna Sepulveda, Sébastien Le Beux, Luo Jiating, Cédric Killian, Daniel Chillet, et al.. Communication Aware Design Method for Optical Network-on-Chip. International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC-15, Sep 2015, Turin, Italy. 2015. <hal-01241858>
  • Singh Rajhans, Daniel Chillet. Intrinsic Fault Tolerance of Hopfield Model for Scheduling Technique in RSoC. International Conference on Neural Computing and Therory Application (NCTA 2014), Oct 2014, Rome, Italy. <hal-01097500>
  • Quang Hai Khuat, Daniel Chillet, Michael Hubner. Considering reconfiguration overhead in scheduling of dependent tasks on 2D Reconfigurable FPGA. International Conference on Adaptive Hardware Systems (AHS 2014), Jul 2014, Leicester, United Kingdom. pp.8, 2014, <http://www2.le.ac.uk/conference/previous/ahs2014>. <hal-01097496>
  • Quang Hai Khuat, Daniel Chillet, Michael Hubner. Dynamic Run-time Hardware/Software Scheduling For 3D Reconfigurable SoC. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2014), Dec 2014, Cancun, Mexico. 2014. <hal-01097509>
  • Quang Hai Khuat, Quang Hoa Le, Daniel Chillet, Sébastien Pillement. Ordonnancement spatio-temporel pour une architecture 3D composée d'une couche multiprocesseur et d'une couche ressource reconfigurables. Conférence d'informatique en Parallélisme, Architecture et Système, Jan 2013, Grenoble, France. pp.ComPAS'2013, 2013. <hal-00808396>
  • Daniel Chillet. Sensibilisation à la modélisation SART pour le développement de code temps réel. CETSIS, l0ème Colloque sur l'Enseignement des. Technologies et des Sciences de l'Information et des Systèmes, Mar 2013, Caen, France. 2013. <hal-00921865>
  • Quang Hai Khuat, Quang Hoa Le, Daniel Chillet, Antoine Courtay, Emmanuel Casseau. Ordonnancement Spatio-Temporel 3D minimisant le coût de communications entre tâches. XXIVe Colloque Gretsi - Traitement du Signal et des Images, Sep 2013, Brest, France. pp.1-7, 2013. <hal-00921867>
  • Quang Hai Khuat, Daniel Chillet. Communication Cost Reduction For Hardware Tasks Placed on Homogeneous Reconfigurable Resource. DASIP 2013, Design and Architectures for Signal and Image Processing, Oct 2013, Cagliari, Italy. pp.265-270, 2013. <hal-00921869>
  • Robin Bonamy, Daniel Chillet, Sebastien Bilavarn, Olivier Sentieys. Power Consumption Model for Partial Dynamic Reconfiguration. International Conference on ReConFigurable Computing and FPGA (RECONFIG'2012), Dec 2012, Cancun, Mexico. 2012. <hal-00741611>
  • Robin Bonamy, Hung-Manh Pham, Sébastien Pillement, Daniel Chillet. UPaRC: Ultra-Fast Power-aware Reconfiguration Controller. Design, Automation and Test in Europe Conference, Mar 2012, Dresden, Germany. pp.1373-1378, 2012. <hal-00741606>
  • Quang Hai Khuat, Quang Hoa Le, Daniel Chillet, Sébastien Pillement. Spatio-Temporal Scheduling for 3D Reconfigurable & Multiprocessor Architecture. Colloque National GDR SoC SiP, Jun 2012, Paris, France. 2012. <hal-00741578>
  • Quang Hai Khuat, Quang Hoa Le, Daniel Chillet, Sébastien Pillement. Spatio-Temporal Scheduling for 3D Reconfigurable and Multiprocessor Architecture. Manifestation des Jeunes Chercheurs en Sciences et Technologies de l'Information et de la Communication, Oct 2012, Lille, France. 2012. <hal-00741612>
  • Daniel Chillet. Estimation et modélisation de la consommation des architectures reconfigurables et du concept de reconfiguration dynamique. Colloque GDR SoC SiP, Jun 2012, Paris, France. 2012. <hal-00741577>
  • Quang Hai Khuat, Quang Hoa Le, Daniel Chillet, Sébastien Pillement. Spatio-Temporal Scheduling for 3D Reconfigurable \& Multiprocessor Architecture. International Design and Test Symposium, IDT 2012, Dec 2012, Doha, Qatar. 2012. <hal-00753902>
  • Robin Bonamy, Hung-Manh Pham, Sébastien Pillement, Daniel Chillet. Power-Aware Ultra-Rapid Reconfiguration Controller. International Conference on Design and Test in Europe, 2012, Dresde, Germany. 2012. <hal-00650592>
  • Daniel Chillet. An Overview of Design Problematics for Embedded Systems. 15th National Symposium on Selected ICT Problems, Dec 2012, Hanoi, Vietnam. 2012. <hal-00759676>
  • Eric Senn, Cécile Belleudy, Daniel Chillet, Rabie Ben Atitallah, Agnès Fritsch, et al.. Open-People: Open-Power and Energy Optimization PLatform and Estimator (Open-People) ANR Project. Forum SAME (Sophia Antipolis Microelectronics), Oct 2012, Sophia Antipolis, France. 2012. <hal-00741608>
  • Eric Senn, Daniel Chillet, Olivier Zendra, Cécile Belleudy, Rabie Ben Atitallah, et al.. Open-People: an Open Platform for Estimation and Optimizations of energy consumption. Design and Architectures for Signal and Image Processing Conference (DASIP 2012), Oct 2012, Karlsruhe, Germany. 2012. <hal-00741609>
  • Daniel Chillet, Eric Senn, Olivier Zendra, Cécile Belleudy, Sebastien Bilavarn, et al.. Open-People: Open Power and Energy Optimization PLatform and Estimator. 15th Euromicro Conference on Digital System Design, Sep 2012, Cesme, Izmir, Turkey. 2012. <hal-00741610>
  • Alexis Pasturel, Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys. Implémentation matérielle d'un réseau de neurones pour l'ordonnancement de tâches sur architectures multi-processeur hétérogènes. Symposium Architectures Nouvelles de Machines, May 2011, Saint Malo, France. 2011. <hal-00650642>
  • Robin Bonamy, Daniel Chillet, Olivier Sentieys, Sebastien Bilavarn. Towards a power and energy efficient use of partial dynamic reconfiguration. Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) Workshop, Jun 2011, Montpellier, France. 2011, <10.1109/ReCoSoC.2011.5981540>. <hal-00650638>
  • Daniel Chillet. JSimRisc : un outil pédagogique pour appréhender le fonctionnement pipeline et quelques techniques avancées mises en oeuvre dans les processeurs récents. Colloque sur l'Enseignement des Technologies et des Sciences de l'Information et des Systèmes, Oct 2011, Trois rivières, Canada. 2011. <hal-00650643>
  • Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys. Parallel Evaluation of Hopfield Neural Networks. NCTA, International Conference on Neural Computation Theory and Applications, Oct 2011, Paris, France. 2011. <hal-00650633>
  • Robin Bonamy, Daniel Chillet, Sebastien Bilavarn, Olivier Sentieys. Parallelism Level Impact on Energy Consumption in Reconfigurable Devices. HEART (International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies), Jun 2011, London, United Kingdom. 2011. <hal-00650631>
  • Daniel Chillet, Antoine Eiche, Sébastien Pillement, Olivier Sentieys. Exploitation du concept de tolérance aux fautes des réseaux de neurones pour la résolution de problèmes d'optimisation. Gretsi, Sep 2011, Bordeaux, France. 2011. <hal-00650634>
  • Robin Bonamy, Daniel Chillet, Sebastien Bilavarn, Olivier Sentieys. Towards a Power and energy Efficient Use of Partial Dynamic Reconfiguration. Colloque GDR SoC/SiP (System On Chip - System In Package), Jun 2011, Lyon, France. 2011. <hal-00650640>
  • Surya Narayanan, Daniel Chillet, Sébastien Pillement, Ionnis Sourdis. Hardware OS Communication Service and Dynamic Hardware OS Communication Service and Dynamic Memory Management for RSoCs. International Conference on ReConFigurable Computing and FPGAs, Nov 2011, Cancun, Mexico. 2011. <hal-00650651>
  • Surya Narayanan, Ludovic Devaux, Daniel Chillet, Sébastien Pillement, Ionnis Sourdis. Communication Service for hardware tasks executed on dynamic and partially reconfigurable substrate. VLSI-SOC, International Conference on Very Large Scale Integration, Oct 2011, Hong-Kong, China. 2011. <hal-00650652>
  • Daniel Chillet, Eric Senn, Cécile Belleudy, Rabie Ben Atitallah, Olivier Zendra, et al.. Open power and energy optimization platform and estimator (open-people). International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2011), Sep 2011, Madrid, Spain. 2011. <hal-00650648>
  • Dominique Blouin, Eric Senn, Robin Bonamy, Daniel Chillet, Sebastien Bilavarn, et al.. FPGA modeling for SoC design exploration. HEART (International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies, Jun 2011, London, United Kingdom. 2011. <hal-00650630>
  • Eric Senn, Jérémie Guillot, Daniel Chillet, Cécile Belleudy, Smail Niar, et al.. Open Power and Energy Optimization Platform and Estimator (Open-People) ANR Project. Design, Automation & Test in Europe (DATE 2011), University Booth, Mar 2011, Grenoble, France. 2011. <hal-00650649>
  • Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys. Task placement for dynamic and partial reconfigurable architecture. Conference on Design and Architectures for Signal and Image Processing, Oct 2010, Edimbourg, United Kingdom. 2010. <inria-00536714>
  • Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny. R2NoC : dynamically Reconfigurable Routers for flexible Networks on Chip. International Conference on ReConFigurable Computing and FPGAs, Dec 2010, Cancun, Mexico. 2010. <inria-00536711>
  • Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny. OS services for Reconfigurable System-on-Chip Communications. Design of Circuits and Integrated Systems, Nov 2010, Lanzarote, Spain. 2010. <inria-00536709>
  • Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny. Mesh and Fat-Tree comparison for dynamically reconfigurable applications. Workshop on Reconfigurable Communication-Centric SoCs (ReCoSoC), May 2010, Karlsruhe, Germany. 2010. <inria-00480548>
  • Sébastien Pillement, Daniel Chillet. High-level Model of Dynamically Reconfigurable Architectures. Conference on Design and Architectures for Signal and Image Processing (DASIP), Sep 2009, Nice, France. 2009. <inria-00446951>
  • Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys. Flot d'ordonnancement pour architecture reconfigurable. Symposium en Architecture de machines (SympA'13), Sep 2009, Toulouse, France. 2009. <inria-00450255>
  • Ludovic Devaux, Sana Ben Sassi, Sébastien Pillement, Daniel Chillet, Didier Demigny. DRAFT: Flexible Interconnection Network for Dynamically Reconfigurable Architectures. IEEE International Conference on Field-Programmable Technology (FPT'09), Dec 2009, Sydney, Australia. 2009. <inria-00446919>
  • Ludovic Devaux, Daniel Chillet, Sébastien Pillement, Didier Demigny. Flexible Communication Support For Dynamically Reconfigurable FPGA. Southern Programmable Logic Conference, Apr 2009, Sao-Carlos, Brazil. pp.65-70, 2009. <inria-00430945>
  • Sébastien Pillement, Daniel Chillet, Yaset Oliva, Jean-Christophe Prévotet. High-Level Exploration for Dynamic Reconfiguration Management. Engineering of Reconfigurable Systems and Algorithms, Jun 2009, Las Vegas, United States. 2009. <inria-00430950>
  • Yaset Oliva, Jean-Christophe Prévotet, Fabienne Nouvel, Sébastien Pillement, Daniel Chillet. Exploration for Dynamic Reconfiguration Management. Sophia Antipolis MicroElectronics Forum, SAME 2009, Sep 2009, Nice, France. 2009. <inria-00446942>
  • Ludovic Devaux, Sana Ben Sassi, Sébastien Pillement, Daniel Chillet, Didier Demigny. Réseau d'interconnexion flexible pour architecture reconfigurable dynamiquement et partiellement. Symposium en Architecture de machines (SympA'13), Sep 2009, Toulouse, France. 2009. <inria-00446921>
  • Daniel Chillet, Sébastien Pillement, Olivier Sentieys. Reconfigurable Artificial Neural Network Model for Task Scheduling on Reconfigurable SoC. Design and Architectures for Signal and Image Processing, Nov 2008, Bruxelles, Belgium. pp.92-99, 2008. <inria-00450262>
  • Erwan Grace, Raphael David, Daniel Chillet, Olivier Sentieys. MOREA : A Memory-Oriented Reconfigurable Embedded Architecture. Design and Architectures for Signal and Image Processing, Nov 2008, Bruxelles, Belgium. pp.124-131, 2008. <inria-00450261>
  • Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Bertrand Granado, Emmanuel Huck, Benoit Miramond, et al.. A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources. ReConFig'08, 2008, Mexico. pp.61-66, 2008. <hal-00404919>
  • Imène Benkermi, Daniel Chillet, Sébastien Pillement, Olivier Sentieys. Hardware Task Scheduling for Heterogeneous SoC Architectures. European Signal Processing Conference (EUSIPCO), 2007, Poznan, Poland. 2007. <inria-00536691>
  • Daniel Chillet, Sébastien Pillement, Olivier Sentieys. Vers une implémentation matérielle d'un réseau de neurones pour le service d'ordonnancement des tâches au sein d'un SoC. Colloque sur le Traitement du Signal et des Images (GRETSI), 2007, Troyes, France. 2007. <inria-00536702>
  • Daniel Chillet, Sébastien Pillement, Olivier Sentieys. A Neural Network Model for Real-Time Scheduling on Heteregeneous SoC Architectures. International Joint Conference on Neural Networks (IJCNN), 2007, Orlando, United States. 2007. <inria-00536722>
  • Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, et al.. Co-Design of Massively Parallel Embedded Processor Architectures. First ReCoSoc workshop, 2005, Montpellier, France. 2005. <hal-00083717>
  • Lahcene Abdelouel, Daniel Chillet, Olivier Sentieys. Synthèse de l'interconnexion des mémoires dans un contexte de système intégré multi-processeurs. Alexandre Vautier, Sylvie Saget. MajecSTIC 2005 : Manifestation des Jeunes Chercheurs francophones dans les domaines des STIC, Nov 2005, Rennes, France. pp.93-99, 2005. <inria-00000675>
  • Imène Benkhermi, Mohamed El Amine Benkhelifa, Daniel Chillet, Sébastien Pillement, Jean-Christophe Prévotet, et al.. System Level Modelling for Reconfigurable SoCs. 20th Conference on Design of Circuits and Integrated Systems (DCIS'05), Nov 2005, Lisboa, Portugal. pp.1, 2005. <hal-00524629>
  • François Verdier, Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Daniel Chillet, Sébastien Pillement. Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. European Workshop on Reconfigurable Communication-centric SoC (ReCoSoC 2005), 2005, Montpellier, France. 2005. <hal-00524777>
  • Daniel Menard, Daniel Chillet, François Charot, Olivier Sentieys. Automatic floating-point to fixed-point conversion for DSP code generation. Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems CASES '02, Nov 2002, Grenoble, France. pp.270--276, 2002, <10.1145/581630.581674>. <inria-00482916>
  • Sébastien Pillement, Olivier Sentieys, Daniel Chillet, Emmanuel Casseau, Philippe Coussy, et al.. Design and synthesis of behavioral level virtual components. 2001, IFIP, pp.23-28, 2001. <hal-00077881>

Poster1 document

  • Jiating Luo, Van Dung Pham, Cedric Killian, Daniel Chillet, Sébastien Le Beux, et al.. POSTER: Wavelength Allocation for Efficient Communications on Optical Network-on-Chip. Conference on Design and Architectures for Signal and Image Processing, Oct 2016, Rennes, France. pp.1656 - 1658, 2016, <10.1145/2810103.2810122>. <hal-01406328>

Pré-publication, Document de travail1 document

  • Robin Bonamy, Sébastien Bilavarn, Daniel Chillet, Olivier Sentieys. Power Modeling and Exploration of Dynamically Reconfigurable Multicore Designs. 2013. <hal-01287838>

HDR1 document

  • Daniel Chillet. Contribution à la gestion dynamique de ressource reconfigurable intégrée au sein d'un MPSoC. Traitement du signal et de l'image. Université Rennes 1, 2010. <tel-00509892v2>

Chapitre d'ouvrage1 document

  • Daniel Chillet, Sébastien Pillement, Olivier Sentieys. RANN: A Reconfigurable Artificial Neural Network Model for Task Scheduling on Reconfigurable System-on-Chip. G. Gogniat and D. Milojevic and A. Morawiec and A. T. Erdogan. Algorithm-Architecture Matching for Signal and Image Processing, Springer Verlag, 2010. <inria-00480545>