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24 résultats
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triés par
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Cache-conscious offline real-time task scheduling for multi-core processors29th Euromicro Conference on Real-Time Systems (ECRTS17), Jun 2017, Dubrovnik, Croatia. ⟨10.4230/LIPIcs.ECRTS.2017.14⟩
Communication dans un congrès
hal-01590421v1
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Scalable Fixed-Point Free Instruction Cache AnalysisThe 32nd IEEE Real-Time Systems Symposium (RTSS 2011), Nov 2011, Vienne, Austria
Communication dans un congrès
inria-00638698v1
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Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faultsDesign, Automation and Test in Europe, Mar 2016, Dresden, Germany
Communication dans un congrès
hal-01259493v1
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The Heptane Static Worst-Case Execution Time Estimation Tool17th International Workshop on Worst-Case Execution Time Analysis (WCET 2017), Jun 2017, Dubrovnik, Croatia. pp.12, ⟨10.4230/OASIcs.WCET.2017.8⟩
Communication dans un congrès
hal-01590444v1
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Static probabilistic Worst Case Execution Time Estimation for architectures with Faulty Instruction Caches21st International Conference on Real-Time Networks and Systems, Oct 2013, Sophia Antipolis, France. ⟨10.1145/2516821.2516842⟩
Communication dans un congrès
hal-00862604v1
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Scheduling of parallel applications on many-core architectures with caches: bridging the gap between WCET analysis and schedulability analysis9th Junior Researcher Workshop on Real-Time Computing (JRWRTC 2015), Nov 2015, Lille, France
Communication dans un congrès
hal-01236191v1
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WCET analysis of multi-level set-associative instruction caches[Research Report] RR-6574, INRIA. 2008
Rapport
inria-00286358v2
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Shared Data Caches Conflicts Reduction for WCET Computation in Multi-Core Architectures.18th International Conference on Real-Time and Network Systems, Nov 2010, Toulouse, France. pp.2283
Communication dans un congrès
inria-00531214v1
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Cache-conscious Off-Line Real-Time Scheduling for Multi-Core Platforms: Algorithms and ImplementationReal-Time Systems, In press, pp.1-37. ⟨10.4230/LIPIcs.ECRTS.2017.14⟩
Article dans une revue
hal-02044110v1
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Quantifying WCET reduction of parallel applications by introducing slack time to limit resource contentionInternational Conference on Real-Time Networks and Systems (RTNS), 2017, Oct 2017, Grenoble, France. ⟨10.475/123_4⟩
Communication dans un congrès
hal-01590532v1
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Ofast3D - Étude de faisabilité[Rapport Technique] RT-0511, Inria Rennes - Bretagne Atlantique; IRISA. 2020, pp.18
Rapport
hal-03093905v1
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The performance vulnerability of architectural and non-architectural arrays to permanent faultsMICRO 45, Dec 2012, Vancouver, Canada
Communication dans un congrès
hal-00747488v1
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An Analytical Framework for Estimating TCO and Exploring Data Center Design SpaceIEEE International Symposium on Performance Analysis of Systems and Software, Apr 2013, Austin, United States
Communication dans un congrès
hal-00914593v1
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Cache-Persistence-Aware Response-Time Analysis for Fixed-Priority Preemptive Systems28th Euromicro Conference on Real-Time Systems (ECRTS), Jul 2016, Toulouse, France. ⟨10.1109/ECRTS.2016.25⟩
Communication dans un congrès
hal-01393220v1
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TRAITOR: A Low-Cost Evaluation Platform for Multifault InjectionASSS '21: Proceedings of the 2021 International Symposium on Advanced Security on Software and Systems, Jun 2021, Virtual Event Hong Kong, Hong Kong SAR China. pp.51-56, ⟨10.1145/3457340.3458303⟩
Communication dans un congrès
hal-03266561v1
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Speeding up Static Probabilistic Timing AnalysisARCS 2015 - International Conference on Architecture of Computing Systems, Mar 2015, Porto, Portugal. pp.236-247, ⟨10.1007/978-3-319-16086-3_19⟩
Communication dans un congrès
hal-01235544v1
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Static Probabilistic Worst Case Execution Time Estimation for Architectures with Faulty Instruction CachesReal-Time Systems, 2015, 51, pp.25. ⟨10.1007/s11241-014-9212-x⟩
Article dans une revue
hal-01086884v1
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WCET ANALYSIS OF MULTI-LEVEL SET-ASSOCIATIVE DATA CACHES9th Intl. Workshop on Worst-Case Execution Time WCET Analysis, Jun 2009, Dublin, Ireland. pp.2283
Communication dans un congrès
inria-00531218v1
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Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches[Research Report] RR-6907, INRIA. 2009
Rapport
inria-00380298v1
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Analyse pire cas pour processeur multi-cœurs disposant de caches partagésRéseaux et télécommunications [cs.NI]. Université Rennes 1, 2010. Français. ⟨NNT : ⟩
Thèse
tel-00557058v1
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NOP-Oriented Programming: Should we Care?Sécurité des Interfaces Logiciel/Matériel, Sep 2020, Genoa (virtual), Italy. ⟨10.1109/EuroSPW51379.2020.00100⟩
Communication dans un congrès
hal-02912301v1
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Estimation of Cache Related Migration Delays for Multi-Core Processors with Shared Instruction Caches17th International Conference on Real-Time and Network Systems, Oct 2009, Paris, France. pp.45-54
Communication dans un congrès
inria-00441959v1
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On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques26th Euromicro Conference on Real-Time Systems, Jul 2014, Madrid, Spain
Communication dans un congrès
hal-01086875v1
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WCET analysis of instruction cache hierarchiesJournal of Systems Architecture, 2011, 57 (7), ⟨10.1016/j.sysarc.2010.08.007⟩
Article dans une revue
istex
hal-00639454v1
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