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76 résultats
Placement de données en mémoire sans conflit pour l'optimisation du réseau d'interconnexion et du contrôleur des entrelaceurs parallèlesColloque GRETSI, Sep 2013, France. pp.xx-yy
Communication dans un congrès
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Prédiction de Branchement dans la Synthèse de Haut NiveauSYMPosium en Architectures, Saint Malo, Mai 2011, May 2011, St Malo, France. pp.XX-YY
Communication dans un congrès
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Improving Storage of Patterns in Recurrent Neural Networks: Clones Based Model and ArchitectureIEEE Int'l Symposium on Circuits & Systems (ISCAS), May 2015, Lisbonne, Portugal
Communication dans un congrès
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Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative MemoriesACM Journal on Emerging Technologies in Computing Systems, 2015, 11 (4), pp.1-23. ⟨10.1145/2629510⟩
Article dans une revue
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Improving Storage of Patterns in Binary Cluster-Based Neural Networks: Clone-based Model and ArchitectureInternationnal workshop on Neural Coding, co-located with DATE Conference 2015, Mar 2015, Grenoble, France
Communication dans un congrès
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A memory Mapping Approach for Parallel Interleaver design with multiples read and write accessesIEEE International Symposium on Circuits and Systems (ISCAS), May 2010, Paris, France. page 3168-3171, ⟨10.1109/ISCAS.2010.5537955⟩
Communication dans un congrès
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A Methodology based on Transportation Problem Modeling for Designing Parallel Interleaver Architectures36th IEEE International Conference on Acoustics, Speech and Signal Processing, May 2011, Prague, Czech Republic. pp.XX-YY
Communication dans un congrès
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Extended RISC-V hardware architecture for future digital communication systems2021 IEEE 4th 5G World Forum (5GWF), Oct 2021, Montreal, Canada. pp.224-229, ⟨10.1109/5GWF52925.2021.00046⟩
Communication dans un congrès
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Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporelsColloque national du GRETSI, Groupe de Recherche et d'Etudes du Traitement du Signal, Sep 2007, Troyes, France
Communication dans un congrès
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A Dynamically Reconfigurable ECC Decoder Architecture for the next generation communication standards (5G, SDR and behond)WInnComm Europe, Oct 2016, Paris, France
Communication dans un congrès
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Clone-Based Encoded Neural Networks to Design Efficient Associative MemoriesIEEE Transactions on Neural Networks and Learning Systems, 2019, 30 (10), pp.1-14. ⟨10.1109/TNNLS.2018.2890658⟩
Article dans une revue
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Improving storage of patterns in recurrent neural networks: Clone-based model and architecture2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 2015, Lisbon, France. pp.577-580, ⟨10.1109/ISCAS.2015.7168699⟩
Communication dans un congrès
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VLSI Architectures and NoCs for Neural Coding1st International Symposium on Brainware LSI, Mar 2014, Japan
Communication dans un congrès
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Designing Parallel Interleaver architecture through Tripartite Edge Coloring ApproachGDR SoC-SiP, Jun 2011, lyon, France
Communication dans un congrès
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An Approach Based on Edge Coloring of Tripartite Graph for Designing Parallel LDPC Interleaver ArchitectureIEEE International Symposium on Circuits and Systems (ISCAS) 2011, May 2011, Rio de Janeiro, Brazil. pp.XX-YY
Communication dans un congrès
hal-00592617v1
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∂ GAUT: A High-Level Synthesis Tool for DSP applicationsPhilippe Coussy & Adam Morawiec. High-Level Synthesis: From Algorithm to Digital Circuits, Springer, pp.147-170, 2008
Chapitre d'ouvrage
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Synthèse automatique d'interfaces de communication matérielles pour la conception d'applications du domaine du traitement du signalAutre [cs.OH]. Université de Bretagne Sud, 2007. Français. ⟨NNT : ⟩
Thèse
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Fully Parallel Circular-Shift Rotation Network for Communication StandardsIEEE Transactions on Circuits and Systems II: Express Briefs, In press, pp.1-1. ⟨10.1109/TCSII.2020.2997691⟩
Article dans une revue
hal-02804289v1
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Amélioration des performances des mémoires associatives par les réseaux à clonesColloque national du GdR SoC-SiP, Jun 2016, Nantes, France
Communication dans un congrès
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In-place memory mapping approach for optimized parallel hardware interleaver architecturesDesign Automation and Test in Europe (DATE 2015), Mar 2015, Grenoble, France
Communication dans un congrès
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A Dynamically Reconfigurable ECC Decoder ArchitectureDesign Automation and Test in Europe (DATE 2016), Mar 2016, Dresden, Germany
Communication dans un congrès
hal-01262057v1
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Apparatus for data interleaving algorithmFrance, Patent n° : 0754793. 2009, pp.10
Brevet
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High-Level Synthesis: On the Path to ESL DesignInternational Conference on ASIC (ASICON 2011), Oct 2011, Xiamen, China
Communication dans un congrès
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A Design Approach Dedicated to Pattern-Based and Conflict-Free Parallel Memory SystemGDR SoC-SiP, Jun 2011, Lyon, France
Communication dans un congrès
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Modèle et Architecture de Réseaux de Neurones Récurrents à ClonesColloque National du GRETSI, Lyon, France, september 2015, Sep 2015, Lyon, France
Communication dans un congrès
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Modélisation de la vision inspirée du vivantJournée prospective: Innover par la voie du biomimétisme, Oct 2014, Rennes, France
Communication dans un congrès
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Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures35th International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2010, Mar 2010, Dallas, United States. Pages: 1594-1597, Paper ID : 2559, ⟨10.1109/ICASSP.2010.5495535⟩
Communication dans un congrès
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Moving to System Level Design Requierements & ChallengesForum on specification & Design Languages, FDL 06, Sep 2006, Darmstadt, Germany
Communication dans un congrès
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GAUT: A High-Level Synthesis Tool for DSP ApplicationsHigh-Level Synthesis : From Algorithm to Digital Circuit, Springer, 2008
Chapitre d'ouvrage
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ON-CHIP IMPLEMENTATION OF MEMORY MAPPING ALGORITHM TO SUPPORT FLEXIBLE DECODER ARCHITECTURE38th International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 2013, France. pp.XX-YY
Communication dans un congrès
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