Nombre de documents

63

CV de Cyrille Chavet


Communication dans un congrès49 documents

  • Cyrille Chavet, Philippe Coussy, Sani Awais Hussein. A Dynamically Reconfigurable ECC Decoder Architecture. Design Automation and Test in Europe, Mar 2016, Dresden, Germany. <hal-01262057>
  • Robin Danilo, Hugues Nono Wouafo, Cyrille Chavet, Philippe Coussy. Associative memory based on clustered neural networks: improved model and architecture for oriented edge detection. Conference on Design & Architectures for Signal & Image Processing, Oct 2016, Rennes, France. Proceedings of Conference on Design & Architectures for Signal & Image Processing. <https://ecsi.org/dasip>. <hal-01364943>
  • Cyrille Chavet, Philippe Coussy. A Dynamically Reconfigurable ECC Decoder Architecture for the next generation communication standards (5G, SDR and behond). WInnComm Europe , Oct 2016, Paris, France. <http://www.europe.wirelessinnovation.org>. <hal-01344550>
  • Hugues Nono, Cyrille Chavet, Philippe Coussy. Amélioration des performances des mémoires associatives par les réseaux à clones. Colloque national du GdR SoC-SiP, Jun 2016, Nantes, France. <hal-01318028>
  • Hugues Nono Wouafo, Cyrille Chavet, Philippe Coussy. Modèle et Architecture de Réseaux de Neurones Récurrents à Clones. Colloque National du GRETSI, Lyon, France, september 2015, Sep 2015, Lyon, France. <hal-01291218>
  • Cyrille Chavet, Hugues Nono Wouafo, Philippe Coussy. Modèle et Architecture de Réseaux de Neurones Récurrents à Clones. Colloque National du GRETSI, Sep 2015, Lyon, France. <hal-01167378>
  • Cyrille Chavet, Hugues Nono Wouafo, Philippe Coussy. Improving Storage of Patterns in Recurrent Neural Networks: Clone-Based Model and Architecture. IEEE International Symposium on Circuits and Systems (ISCAS) 2015, May 2015, Lisbonne, Portugal. 2015. <hal-01167364>
  • Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy. In-place memory mapping approach for optimized parallel hardware interleaver architectures. DATE 2015, Mar 2015, Grenoble, France. <hal-01101586>
  • Hugues Nono Wouafo, Cyrille Chavet, Philippe Coussy. Improving Storage of Patterns in Binary Cluster-Based Neural Networks: Clone-based Model and Architecture. Internationnal workshop on Neural Coding, co-located with DATE Conference 2015, Mar 2015, Grenoble, France. 2015. <hal-01101583>
  • Hugues Nono Wouafo, Cyrille Chavet, Philippe Coussy. Improving Storage of Patterns in Recurrent Neural Networks: Clones Based Model and Architecture. IEEE Int'l Symposium on Circuits & Systems (ISCAS), May 2015, Lisbonne, Portugal. 2015. <hal-01101580>
  • Jean-Philippe Diguet, Philippe Coussy, Cyrille Chavet. VLSI Architectures and NoCs for Neural Coding. 1st International Symposium on Brainware LSI, Mar 2014, Japan. <hal-01009489>
  • Cyrille Chavet, Philippe Coussy, Saeed Ur Reehman. A Memory Mapping Approach based on Network Customization to Design Conflict-Free Parallel Hardware Architectures. ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2014, France. pp.xx-yy, 2014. <hal-01009477>
  • Saeed Ur Reehman, Awais Hussein Sani, Philippe Coussy, Cyrille Chavet. Embedding Polynomial Time Memory Mapping and Routing Algorithms on-chip to Design Configurable Decoder Architecture. IEEE International Conference on Acoustics, Speech and Signal Processing, May 2014, Italy. pp.xx-yy, 2014. <hal-01009478>
  • Cyrille Chavet, Philippe Coussy. Modélisation de la vision inspirée du vivant. Journée prospective: Innover par la voie du biomimétisme, Oct 2014, Rennes, France. <hal-01079094>
  • Philippe Coussy, Cyrille Chavet. Modélisation de la vision inspirée du vivant. Journée prospective: Innover par la voie du biomimétisme, Oct 2014, Rennes, France. <hal-01079098>
  • Mickael Lanoe, Bordin Matteo, Dominique Heller, Cyrille Chavet, Philippe Coussy. A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code. 21st IEEE International Conference on Electronics Circuits and Systems, Dec 2014, Marseille, France. 2014. <hal-01069265>
  • Cyrille Chavet, Philippe Coussy, Saeed Ur Reehman. Designing optimized parallel interleaver architecture through network customization. Colloque national du GdR SoC-SiP, Jun 2014, France. <hal-01009679>
  • Aroua Briki, Cyrille Chavet, Philippe Coussy. A CONFLICT-FREE MEMORY MAPPING APPROACH TO DESIGN PARALLEL HARDWARE INTERLEAVER ARCHITECTURES WITH OPTIMIZED NETWORK AND CONTROLLER. IEEE Workshop on Signal Processing Systems (SiPS), Oct 2013, Taipei, Taiwan. pp.xx-yy, 2013. <hal-00861312>
  • Aroua Briki, Cyrille Chavet, Philippe Coussy. A Memory Mapping Approach for Network and Controller Optimization in Parallel Interleaver Architectures. 23rd edition of Great Lake symposium on VLSI, May 2013, Paris, France. pp.XX-YY, 2013. <hal-00799762>
  • Sani Awais Hussein, Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy. ON-CHIP IMPLEMENTATION OF MEMORY MAPPING ALGORITHM TO SUPPORT FLEXIBLE DECODER ARCHITECTURE. 38th International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 2013, France. pp.XX-YY, 2013. <hal-00799771>
  • Vianney Lapotre, Philippe Coussy, Cyrille Chavet, Hugues Nono Wouafo, Robin Danilo. Dynamic Branch Prediction For High-Level Synthesis. International Conference on Field Programmable Logic and Applications, Sep 2013, Portugal. pp.XX-YY, 2013. <hal-00830417>
  • Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin. Placement de données en mémoire sans conflit pour l'optimisation du réseau d'interconnexion et du contrôleur des entrelaceurs parallèles. Colloque GRETSI, Sep 2013, France. pp.xx-yy, 2013. <hal-00830418>
  • Paolo Burgio, Marongiu Andrea, Luca Benini, Cyrille Chavet, Philippe Coussy, et al.. OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters. 15th Euromicro Conference on Digital System Design: Architectures, Methods & Tools, Sep 2012, Turkey. pp.XX-YY, 2012. <hal-00721366>
  • Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin. A Design Approach to generate optimized parallel hard- ware interleaver architecture. Colloque nationnale du GdR CoC-SiP, Jun 2012, France. <hal-00721372>
  • Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin. A Design Approach Dedicated to Network-Based and Conflict-Free Parallel Interleavers. GLS-VLSI conference, May 2012, United States. pp.XX-YY, 2012. <hal-00721375>
  • Paolo Burgio, Marongiu Andrea, Luca Benini, Cyrille Chavet, Philippe Coussy, et al.. Automated Synergistic Parallelization and HW Accele- ration for On-Chip Shared-Memory Clusters. Colloque nationnale du GdR Soc-SiP, Jun 2012, France. <hal-00721370>
  • Oscar Sanchez, Sani Awais Hussein, Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy, et al.. Dedicated approach to explore design space for hardware architecture of turbo decoders. IEEE Workshop on Signal Processing Systems, Oct 2012, Canada. pp.XX-YY, 2012. <hal-00721379>
  • Philippe Coussy, Cyrille Chavet, Dominique Heller. High-Level Synthesis: On the Path to ESL Design. International Conference on ASIC (ASICON 2011), Oct 2011, Xiamen, China. 2011. <hal-00661720>
  • Sani Awais Hussein, Philippe Coussy, Cyrille Chavet, Eric Martin. An Approach Based on Edge Coloring of Tripartite Graph for Designing Parallel LDPC Interleaver Architecture. IEEE International Symposium on Circuits and Systems (ISCAS) 2011, May 2011, Rio de Janeiro, Brazil. pp.XX-YY, 2011. <hal-00592617>
  • Sani Awais Hussein, Philippe Coussy, Cyrille Chavet, Eric Martin. A Methodology based on Transportation Problem Modeling for Designing Parallel Interleaver Architectures. 36th IEEE International Conference on Acoustics, Speech and Signal Processing, May 2011, Prague, Czech Republic. pp.XX-YY, 2011. <hal-00592669>
  • Vianney Lapotre, Philippe Coussy, Cyrille Chavet. Prédiction de Branchement dans la Synthèse de Haut Niveau. SYMPosium en Architectures, Saint Malo, Mai 2011, May 2011, St Malo, France. pp.XX-YY, 2011. <hal-00592606>
  • Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin. A Design Approach Dedicated to Pattern-Based and Conflict-Free Parallel Memory System. GDR SoC-SiP, Jun 2011, Lyon, France. <hal-00682198>
  • Sani Awais Hussein, Cyrille Chavet, Philippe Coussy, Eric Martin. Designing Parallel Interleaver architecture through Tripartite Edge Coloring Approach. GDR SoC-SiP, Jun 2011, lyon, France. <hal-00682201>
  • Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard. Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures. 35th International Conference on Acoustics, Speech, and Signal Processing (ICASSP) 2010, Mar 2010, Dallas, United States. Pages: 1594-1597, Paper ID : 2559, 2010, <10.1109/ICASSP.2010.5495535>. <hal-00455121>
  • Sani Awais Hussein, Philippe Coussy, Cyrille Chavet, Eric Martin. A Bipartite Edge Coloring Approach for designing Parallel Interleaver architecture. Colloque nationnale du GDR SoC-SiP, Jun 2010, France. <hal-00495368>
  • Awais Hussein Sani, Philippe Coussy, Cyrille Chavet, Eric Martin. Design of Parallel LDPC Interleaver Architecture: A Bipartite Edge Coloring Approach. IEEE International Conference on Electronics, Circuits, and Systems, Athens, Greece (ICECS) 2010, Dec 2010, Athens, Greece. pp.XX-YY, 2010. <hal-00551432>
  • Cyrille Chavet, Philippe Coussy. A memory Mapping Approach for Parallel Interleaver design with multiples read and write accesses. IEEE International Symposium on Circuits and Systems (ISCAS), May 2010, Paris, France. page 3168-3171, 2010, <10.1109/ISCAS.2010.5537955>. <hal-00482682>
  • Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin. Design space exploration tool for Space-Time AdapteRs. Workshop The new wave of High Level Synthesis, in Design, Automation and Test in Europe (DATE), Mar 2008, Munich, Germany. <hal-00554678>
  • Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin. Design Methodology for Efficient Space Time AdapteR. PhD forum, in Design, Automation and Test in Europe (DATE), Mar 2008, Munich, Germany. <hal-00554680>
  • Cyrille Chavet, C. Andriamisaina, Philippe Coussy, E. Casseau, E. Juin, et al.. A Design Flow Dedicated to Multi-mode Architectures for DSP Applications. International Conference on Computer Aided Design, Nov 2007, United States. IEEE, pp.604 - 611, 2007. <hal-00167927>
  • Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard. Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels. Colloque national du GRETSI, Groupe de Recherche et d'Etudes du Traitement du Signal, Sep 2007, Troyes, France. <hal-00490210>
  • Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin. A Design Methodology for Space-Time Adapter. ACM SICDA. ACM Great Lakes Symposium on VLSI 2007, Mar 2007, Stresa, Italy. ACM SICDA, pp.347, 2007. <hal-00153789>
  • Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin. A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver. IEEE. The IEEE International Symposium on Circuits and Systems (ISCAS), May 2007, New Orleans, United States. Library of Congress, pp.2946-2949, 2007, <10.1109/ISCAS.2007.377867>. <hal-00153994>
  • Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin. Application of a design space exploration tool to enhance interleaver generation. European Signal Processing Conference (EUSIPCO-2007), Sep 2007, Poznan, Poland. Eurasip, pp.XX-YY, 2007. <hal-00154025>
  • Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard. Methodologie de synthèse d'adaptateurs spatio-temporels. Colloque national du GDR SoC-SiP, Jun 2007, Paris, France. <hal-00369164>
  • Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard. Methodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels. GRETSI - Groupe de Recherche et d'Etudes du Traitement du Signal et des Images, Sep 2007, Troyes, France. pp.XX-YY, 2007. <hal-00369167>
  • Cyrille Chavet. Moving to System Level Design Requierements & Challenges. Forum on specification & Design Languages, FDL 06, Sep 2006, Darmstadt, Germany. 2006. <hal-00369143>
  • Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin. Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels. Alexandre Vautier, Sylvie Saget. MajecSTIC 2005 : Manifestation des Jeunes Chercheurs francophones dans les domaines des STIC, Nov 2005, Rennes, pp.151-158, 2005. <inria-00000699>
  • Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin. Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels. Manisfestation des jeunes chercheurs en STIC, Nov 2005, Rennes, France. No, pp.151, 2005. <hal-00154014>

Direction d'ouvrage, Proceedings2 documents

  • Cyrille Chavet, Philippe Coussy. Advanced Hardware Design for Error Correcting Codes. Springer, pp.200, 2014. <hal-01009474>
  • Bordin Matteo, Mickael Lanoe, Dominique Heller, Cyrille Chavet, Philippe Coussy. A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code. 21st IEEE International Conference on Electronics Circuits & Systems, Dec 2014, Marseille, France. 2014. <hal-01075807>

Chapitre d'ouvrage3 documents

  • Cyrille Chavet, Philippe Coussy. Hardware design of parallel interleaver architecture: a survey. Advanced Hardware Design for Error Correcting Codes, Springer, pp.xx-yy, 2014. <hal-01009476>
  • Eric Senn, Philippe Coussy, Cyrille Chavet, Pierre Bomel, Dominique Heller. GAUT: A High-Level Synthesis Tool for DSP Applications. High-Level Synthesis : From Algorithm to Digital Circuit, Springer, 2008. <hal-00489794>
  • Philippe Coussy, Cyrille Chavet, Pierre Bomel, Dominique Heller, Eric Senn, et al.. ∂ GAUT: A High-Level Synthesis Tool for DSP applications. Philippe Coussy & Adam Morawiec. High-Level Synthesis: From Algorithm to Digital Circuits, Springer, pp.147-170, 2008. <hal-00369029>

Article dans une revue4 documents

  • Philippe Coussy, Cyrille Chavet, Laura Conde Canencia, Hugues Nono Wouafo. Fully-Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories. ACM Journal on Emerging Technologies in Computing Systems, Association for Computing Machinery, 2014, pp.xx-yy. <hal-01009473>
  • Vianney Lapotre, Philippe Coussy, Cyrille Chavet. Introduction de la prédiction de branchement dans la synthèse de haut niveau. Technique et Science Informatiques, Editions Hermes, 2013, pp.XX-YY. <hal-00799808>
  • Awais Hussein Sani, Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy. A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm. IEEE Transaction on Signal Processing, IEEE Signal Processing Society, 2013, pp.xx-yy. <hal-00820779>
  • Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Cyrille Chavet. High-Level Synthesis for Designing Multimode Architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2010, 29 (11), pp.1736. <hal-00551454>

Brevet4 documents

  • Cyrille Chavet, Philippe Coussy, Jean-Philippe Diguet, John Shield. Système de traitement de données avec cache actif. N° de brevet: 1256715. 2014. <hal-00776063>
  • Cyrille Chavet, Philippe Coussy, Nicolas Charpentier. Architecture de réseau de neurone, procédé d'obtention et programmes correspondants. France, N° de brevet: 1261155. 2014. <hal-00776062>
  • Cyrille Chavet, Philippe Coussy. Dispositif auto-configurable d'entrelacement/désentrelacement de trames de données. N° de brevet: 1251688. 2013. <hal-00749589>
  • Cyrille Chavet, Philippe Coussy, Eric Martin, Pascal Urard. Apparatus for data interleaving algorithm. France, Patent n° : 0754793. 2009, pp.10. <hal-00369159>

Thèse1 document

  • Cyrille Chavet. Synthèse automatique d'interfaces de communication matérielles pour la conception d'applications du domaine du traitement du signal. Autre [cs.OH]. Université de Bretagne Sud, 2007. Français. <tel-00369043>