Accéder directement au contenu

Claudio Lazzari

11
Documents
Identifiants chercheurs

Présentation

Publications

lorena-anghel

An Analysis and Design Technique to Reduce SET Sensitivity in Combinational Integrated Circuits

C. Lazzari , T. Assis , F. Kastensmidt , G. Wirth , Lorena Anghel
16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-Soc'08), Oct 2008, Rhodes Island, Greece. pp.114-117
Communication dans un congrès hal-01408783v1

SET-Factor: An Analysis and Design Tool to Reduce SET Sensitivity in Integrated Circuits

C. Lazzari , T. Assis , F. Kastensmidt , G. Wirth , Lorena Anghel
13th IEEE European Test Symposium (ETS'08), May 2008, Verbania, Italy
Communication dans un congrès hal-01408791v1

Efficient Timing Closure with a Transistor Level Design Flow

C. Lazzari , Cr. Santos , A. Ziesemer , Lorena Anghel , Ricardo Reis
IFIP International Conference on Very Large Scale Integration (VLSI-SoC'07), Oct 2007, Atlanta, GA, United States. pp.312-315
Communication dans un congrès hal-01408793v1

Efficient Transistor Sizing for Soft Error Protection in Combinational Logic Circuits

C. Lazzari , F. Lima , Lorena Anghel , Ricardo Reis
2nd International Workshop on Dependable Circuit Design (DECIDE’07), Dec 2007, Buenos Aires, Argentina
Communication dans un congrès hal-01408792v1

SET fault injection methods in analog circuits: case study

A. Ammari , Lorena Anghel , Régis Leveugle , C. Lazzari , Ricardo Reis
8th Latin-American Test Workshop (LATW'07), Mar 2007, Cuzco, Peru. pp.155-160
Communication dans un congrès hal-00156749v1

Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study

C. Lazzari , Ricardo Reis , Lorena Anghel
12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006, Lake Como, Italy. pp.165-172, ⟨10.1109/IOLTS.2006.48⟩
Communication dans un congrès hal-00143423v1

Multiple Defects Tolerant Devices for Unreliable Future Nanotechnologies

C. Lazzari , Lorena Anghel , M. Nicolaidis
IEEE Latin American Test Workshop (LATW'06), Mar 2006, Buenos Aires, Argentina
Communication dans un congrès hal-01408796v1

On implementing a soft error hardening technique by using an automatic layout generator: case study

C. Lazzari , Lorena Anghel , Ricardo Reis
11th-IEEE-International-On-Line-Testing-Symposium., 2005, French Riviera, France. pp.29-34, ⟨10.1109/IOLTS.2005.45⟩
Communication dans un congrès hal-00015449v1

Soft error circuit hardening techniques implementation using an automatic layout generator

C. Lazzari , Lorena Anghel , Ricardo Reis
Proceedings of IEEE Latin American Test Workshop (LATW'05), Mar 2005, Salvador Bahia, Brazil. pp.175-180
Communication dans un congrès hal-00460557v1

A Transistor Placement Technique Using Genetic Algorithm And Analytical Programming

C. Lazzari , Lorena Anghel , Ricardo Reis
VLSI-SOC: From Systems to Silicon, (selected contributions from VLSI-SoC'05), Springer, pp.331-344, Vol.240, 2007, Series: IFIP International Federation for Information Processing, ⟨10.1007/978-0-387-73661-7_21⟩
Chapitre d'ouvrage hal-00191996v1